CN8478/CN8474A/CN8472A/CN8471A
4.0 Serial Interface
Multichannel Synchronous Communications Controller (MUSYCC™) 4.7 Tx and Rx FIFO Buffer Allocation and Manage-
4.7 Tx and Rx FIFO Buffer Allocation and
Management
Each channel group contains a separate internal buffer memory space for transmit
and receive operations. Within each of these spaces, separate areas are set aside
for specific functions.
Each channel within the group must be allocated buffer space before the
channel can be activated. Table 4-2 lists the internal buffer memory allocation.
This space acts as a holding buffer for incoming (Rx) and outgoing (Tx) data.
Data buffers for each channel are allocated using the BUFFLOC and BUFFLEN
bit fields (Table 5-18, Channel Configuration Descriptor). Both receiver and
transmitter of a channel use a data buffer scheme where half the available FIFO
services the serial interface, and the other half services data in shared memory.
Figures 4-6 and 4-7 illustrate the receive and transmit data flows, respectively.
BUFFLEN+1 specifies half the size of the buffer space allocated to a direction of
the channel.
Table 4-2. Internal Buffer Memory Layout
Memory Area
Transmit
Receive
Fixed Data Buffer
64 dwords
64 dwords
64 dwords
64 dwords
Subchannel Map
(or Additional Data Buffer if No Subchanneling)
Time Slot Map
Total
32 dwords
32 dwords
160 dwords
640 bytes
160 dwords
640 bytes
Figure 4-6. Receive Data Flow
Control
1/2 FIFO
Receive
Channel
Shared
Memory
BLP
DMAC
Data
Data
PCI
Bus
1/2 FIFO
Internal Data Buffer
8478_018
NOTE(S): 1/2 FIFO = BUFFLEN+1
100660E
Conexant
4-11
CONEXANT [ CONEXANT SYSTEMS, INC ]
