4.0 Serial Interface
CN8478/CN8474A/CN8472A/CN8471A
4.5 Channelized Port Mode
Multichannel Synchronous Communications Controller (MUSYCC™)
supporting an Nx8 bit rate between 8 kbps to 64 kbps in multiples of 8 kbps. The
following configurations are required to support subchannels:
•
Each active bit is assigned a logical channel number within a channel
group (0–31).
•
•
Each time slot with active bits must be enabled in the Time Slot Map.
Each active bit (after the first bit, bit 0) must be enabled in the Subchannel
Map.
The Time Slot Descriptor (Table 5-15), and the Subchannel Descriptor
(Table 5-17), enable and assign a time slot and each individual bit within the time
slot to a logical channel. The configurations for receive and transmit subchannels
are independent.
The Time Slot Descriptor assigns bit 0 of a time slot to a logical channel. The
Subchannel Descriptor assigns bits 1 through 7 of a time slot to a logical channel.
4.5.3 Frame Synchronization Flywheel
MUSYCC utilizes the TSYNC and RSYNC signals to maintain a timebase which
keeps track of the active bit in the current time slot. The mechanism is referred to
as the frame synchronization flywheel. The flywheel counts the number of bits
per frame and automatically rolls over the bit count according to the programmed
mode. The TSYNC or RSYNC input marks the first bit in the frame. The mode
specified in the PORTMD bit field (Table 5-12, Port Configuration Descriptor),
determines the number of bits in the frame. A flywheel exists for both the
transmit and receive functions for every port.
The flywheel is synchronized when MUSYCC detects TSYNC = 1 or
RSYNC = 1, for transmit or receive functions, respectively. Once synchronized,
the flywheel maintains synchronization without further assertion of the
synchronization signal.
A time slot counter within each port is reset at the beginning of each frame
and tracks the current time slot being serviced.
For the Nx64 mode, the value of N cannot be specified; therefore, the data
requires a synchronization pulse every frame period to reset the flywheel. Also, in
Nx64 mode, the TSYNC must precede the output of bit 0 of the frame by four line
clock periods.
Figures 4-2 through 4-4 illustrate the timing relationships between the data
and the synchronization signal for various modes of operation.
4-4
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
