3.0 Expansion Bus (EBUS)
CN8478/CN8474A/CN8472A/CN8471A
3.1 Operation
Multichannel Synchronous Communications Controller (MUSYCC™)
3.1.9 Microprocessor Interface
The MPUSEL bit field specifies the type of microprocessor interface to use for
the EBUS. (See Table 5-6, Global Configuration Descriptor.)
Table 3-1 describes the effective signals when Intel-style protocol is selected.
Table 3-1. Intel Protocol Signals
Signal
Description
Interpretation
ALE*
Address Latch Enable
Asserted low by MUSYCC to indicate that the
address lines contain a valid address. This signal
remains asserted for the duration of the access
cycle.
RD*
Read
Strobed low by MUSYCC to enable data reads out of
the device. Held high during writes.
WR*
HOLD
HLDA
Write
Strobed low by MUSYCC to enable data writes into
the device. Held high during reads.
Hold Request
Hold Acknowledge
Asserted high by MUSYCC when it requests the
EBUS from a bus arbiter.
Asserted high by bus arbiter in response to HOLD
signal assertion. Remains asserted until after the
HOLD signal is deasserted. If the EBUS is connected
and there are no bus arbiters on the EBUS, this
signal must be asserted high at all times.
NOTE(S): An active low signal is denoted by a trailing asterisk (*).
3-6
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
