CN8478/CN8474A/CN8472A/CN8471A
2.0 Host Interface
Multichannel Synchronous Communications Controller (MUSYCC™)
2.1 PCI Interface
Table 2-1. Function 0 Configuration Space
Register
Number
Byte Offset
(Hex)
31
24
16
8
0
Device ID(1)
Status
Vendor ID(1)
Command
0
00h
1
2
04h
08h
Revision ID(1)
Base Code
Header Type
3
4
0Ch
10h
14h
—
Reserved
LatencyTimer
Reserved
MUSYCC Base Address Register (BAR)
5
—
Reserved
—
—
14
15
38h
3Ch
Max Latency
Min Grant
Interrupt Pin
Interrupt Line
NOTE(S):
(1)
Registers shared between Function 0 and 1.
Table 2-2. Function 1 Configuration Space
Register
Number
Byte Offset
(Hex)
31
24
16
8
0
Device ID(1)
Status
Vendor ID(1)
Command
Revision ID(1)
0
00h
1
2
04h
08h
Base Code
3
4
0Ch
10h
14h
—
Reserved
Header Type
Reserved
Reserved
EBUS Base Address Register (BAR)
5
—
Reserved
—
—
14
15
38h
3Ch
Reserved
Interrupt Pin
Interrupt Line
NOTE(S):
(1)
Registers shared between Function 0 and 1.
100660E
Conexant
2-5