1.0 System Description
CN8478/CN8474A/CN8472A/CN8471A
1.1 Pin Descriptions
Multichannel Synchronous Communications Controller (MUSYCC™)
Table 1-4. CN8478 Hardware Signal Definitions (2 of 6)
MQFP
Pin No.
Pin Label
Signal Name
I/O
Definition
Transmit Clock (1)
117, 122,
125, 128,
131, 136,
140, 143
TCLK[7:0]
I
Controls the rate at which data is transmitted. Synchronizes
transitions for TDATx and sampling of TSYNCx. Valid frequencies
from DC to 8.192 ±10% MHz. Schmitt trigger driver.
116, 121, TSYNC[7:0] Transmit
I
TSYNC is sampled on the specified active edge of the
corresponding transmit clock, TCLKx. See TSYNC_EDGE bit field
in Table 5-12.
Synchronization (1)
124, 127,
130, 135,
139, 142
As TSYNCx signal transitions low-to-high, start of a transmit
frame is indicated. For T1 mode, the corresponding data bit
latched out during the same bit time period (but not necessarily
the same clock edge) is the F-bit of the T1 frame. For E1 modes,
the corresponding data bit latched out during the same bit time
period (but not necessarily the same clock edge) is bit 0 of the E1
frame. For Nx64 mode, the corresponding data bit is latched out
4-bit time periods later and is bit 0 of the Nx64 frame.
TSYNCx must remain asserted high for a minimum of a setup
and hold time relative to the active clock edge for this signal. If
the flywheel mechanism is used, no other synchronization signal
is required, because MUSYCC tracks the start of each
subsequent frame. If the flywheel mechanism is not used, then a
subsequent low-to-high assertion is required to indicate the start
of the next frame. See SFALIGN bit field in Table 5-10.
115, 120,
123, 126,
129, 134,
138, 141
TDAT[7:0] Transmit Data
t/s O Serial data latched out on active edge of transmit clock, TCLKx. If
channel is unmapped to time slot, data bit is considered invalid
and MUSYCC outputs either three-state signal or logic 1
depending on value of bit field TRITX in Table 5-12.
Receive Clock (1)
4, 8, 12,
18, 22,
26, 32,
208
RCLK[7:0]
I
Active edge samples RDATx and RSYNCx. Valid frequencies from
DC to 8.192 10% MHz. Schmitt trigger driver.
1, 5, 9,
15, 19,
23, 29, 33
RSYNC[7:0] Receive
Synchronization (1)
I
RSYNCx is sampled on the specified active edge of the
corresponding receive clock, RCLKx. See RSYNC_EDGE bit field
in Table 5-12.
As RSYNCx signal transitions low-to-high, start of a receive
frame is indicated. For T1 mode, the corresponding data bit
sampled and stored during the same bit time period (but not
necessarily the same clock edge) is the F-bit of the T1 frame. For
E1 modes, the corresponding data bit sampled and stored during
the same bit time period (but not necessarily the same clock
edge) is bit 0 of the E1 frame. For Nx64 mode, the corresponding
data bit sampled and stored during the same bit time period (but
not necessarily the same clock edge) is bit 0 of the Nx64 frame.
RSYNCx must be asserted high for a minimum of a setup and
hold time relative to the active clock edge for this signal. If the
flywheel mechanism is used, no other synchronization signal is
required, because MUSYCC tracks the start of each subsequent
frame. If the flywheel mechanism is not used, a subsequent
low-to-high assertion is required to indicate the start of the next
frame. See SFALIGN bit field in Table 5-10.
1-20
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
