CN8478/CN8474A/CN8472A/CN8471A
5.0 Memory Organization
Multichannel Synchronous Communications Controller (MUSYCC™)
5.2 Descriptors
Table 5-16. Transmit or Receive Subchannel Map
Byte Offset
MSB
LSB
00h
04h
08h
0Ch
...
Ch0, Bit 3
Ch0, Bit 7
Ch1, Bit 3
Ch1, Bit 7
....
Ch0, Bit 2
Ch0, Bit 6
Ch1, Bit 2
Ch1, Bit 6
....
Ch0, Bit 1
Ch0, Bit 5
Ch1, Bit 1
Ch1, Bit 5
....
Unused
Ch0, Bit 4
Unused
Ch1, Bit 4
...
...
....
....
....
...
F8h
FCh
Ch31, Bit 3
Ch31, Bit 7
Ch31, Bit 2
Ch31, Bit 6
Ch31, Bit 1
Ch31, Bit 5
Unused
Ch31, Bit 4
Table 5-17. Subchannel Descriptor
Bit Field
Name
Value
Description
31
BITEN3/7
0
Bit disabled.
1
Bit enabled.
Reserved.
30:29
28:24
23
RSVD
0
CH3[4:0]
BITEN2/6
0–31
Channel number assigned to this bit.
Bit disabled.
0
1
Bit enabled.
22:21
20:16
15
RSVD
0
Reserved.
CH2[4:0]
BITEN1/5
0–31
Channel number assigned to this bit.
Bit disabled.
0
1
0
Bit enabled.
14:13
12:8
7
RSVD
Reserved.
CH1[4:0]
BITEN0/3
0–31
0
Channel number assigned to this bit.
Bit disabled.
1
Bit enabled.
6:5
4:0
RSVD
0
Reserved.
CH0[4:0]
0–31
Channel number assigned to this bit.
To enable the subchanneling feature, both the Time Slot Map and the
Subchannel Map must be copied into MUSYCC’s internal registers because it is
from here time slot-to-channel mapping and channel-to-subchannel mapping is
decoded. The host can instruct MUSYCC to read in the maps from shared
memory by issuing the appropriate service request; otherwise, the host must
perform multiple direct writes into MUSYCC’s internal registers by appropriately
addressing PCI access cycles for MUSYCC.
100660E
Conexant
5-25
CONEXANT [ CONEXANT SYSTEMS, INC ]
