6.0 Basic Operation
CN8478/CN8474A/CN8472A/CN8471A
6.2 Configuration
Multichannel Synchronous Communications Controller (MUSYCC™)
6.2.6 MUSYCC Internal Memory
MUSYCC has two areas of host-accessible internal memories. One is the Internal
RAM (IRAM) and is accessed through MUSYCC’s Direct Memory Access
Controller (DMAC). The IRAM area contains the following descriptors and
maps:
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Table 5-14, Transmit or Receive Time Slot Map
Table 5-16, Transmit or Receive Subchannel Map
Table 5-18, Channel Configuration Descriptor (transmit or receive)
A second area of internal memories makes up the Host Interface registers.
This area is not accessed through MUSYCC’s DMAC. The Host Interface register
contains the following descriptors:
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Table 5-6, Global Configuration Descriptor
Table 5-7, Dual Address Cycle Base Pointer
Table 5-8, Group Base Pointer
Table 5-9, Service Request Descriptor
Table 5-10, Group Configuration Descriptor
Table 5-11, Memory Protection Descriptor
Table 5-12, Port Configuration Descriptor
Table 5-13, Message Length Descriptor
Table 5-14, Transmit or Receive Time Slot Map
Table 5-16, Transmit or Receive Subchannel Map
Table 5-18, Channel Configuration Descriptor
Table 5-28, Interrupt Queue Descriptor
6.2.6.1 Memory
Operations—Inactive
Channels
When all channels are deactivated, the IRAM and Host Interface registers can be
read and written. The IRAM registers require that the corresponding channel
group’s line clocks (TCLK, RCLK) are active. Reading from any IRAM register
with inactive line clocks returns the pattern DEAD ACCEh—conveying "dead
access". Writing to any IRAM register with inactive line clocks returns in the
writes being ignored.
Read operations to invalid (unsupported to reserved) addresses or write-only
registers return all 1s. Write operations to invalid (unsupported or reserved)
addresses or read-only register bits result in the write to that bit location being
ignored.
6.2.6.2 Memory
Operations—Active
Channels
There are only a few locations that are allowed to be slave-accessed after
MUSYCC has an active channel:
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Group Base Pointer
Service Request Descriptor
Interrupt Status Descriptor
Any EBUS function 1 location
The host must not perform PCI slave accesses to any other register after
MUSYCC has a channel activated on any group. Any attempt to read or write to
other MUSYCC registers as a PCI slave device while channels are activated can
result in DMAC lock-up and spontaneous (unreported) channel deactivation.
This limitation is inclusive of all groups; for example, it is not acceptable to
perform a slave write to the group 2 time slot map while there is an active channel
on group 0.
6-6
Conexant
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CONEXANT [ CONEXANT SYSTEMS, INC ]
