7.0 Electrical and Mechanical Specifications
CN8478/CN8474A/CN8472A/CN8471A
7.2 Timing and Switching Specifications
Multichannel Synchronous Communications Controller (MUSYCC™)
Figure 7-10. EBUS Reset Timing
PCI
Reset
Reset Period
Toff
EBUS
Three-state
Output
Three-state
EBUS
Input
Input Ignored
8478_032
NOTE(S): The EBUS reset is dependent on the PRST* (PCI Reset) signal being asserted low.
Table 7-12. EBUS I/O Timing Parameters
Symbol
Tval
Parameter
Min
Max
Units
PCI Clock Fall to Signal Valid Delay—Bused
Signal(1)
2
15
ns
Tval (ptp)
PCI Clock Fall to Signal Valid Delay—Point To
Point(1)
2
15
ns
Float to Active Delay(2)
Ton
—
—
3
30
30
—
—
—
7
ns
ns
ns
ns
ns
ns
Active to Float Delay(2)
Toff
Tds
Input Setup Time to Clock—Bused Signal
Tds (ptp)
Tdh
Input Setup Time to Clock—Point To Point
Input Hold Time from Clock
3
7
Tde
PCI Clock Fall to ECLK rising edge
—
NOTE(S):
(1)
Minimum and maximum times are evaluated at 80 pF equivalent load. Actual test capacitance may vary, and results should
be correlated to these specifications.
For purposes of active/float timing measurements, the hi-z or off state is when the total current delivered through the
component pin is less than or equal to the leakage current specification at 80 pF equivalent load.
(2)
7-12
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
