CN8223
2.0 Functional Description
ATM Transmitter/Receiver with UTOPIA Interface
2.6 ATM Cell Processing
2.6.4 PLCP Cell Validation for Receive
In 57-octet PLCP formats, the PHY receiver implements framing state machines
for cell alignment as described in TR-TSV-000773. In 53-octet formats, the PHY
receiver implements the HEC alignment state machine as described in ITU I.432.
In serial framed 57-octet mode, the PHY receiver processes a serial stream to
find PLCP framing. Octet synchronization is provided externally in DS1 and E1
modes. Internal or external E3 octet synchronization and DS3 nibble
synchronization are provided to the PHY framer. Physical layer framing patterns
are automatically removed before recovery of the octet data. If unframed mode is
enabled, the receiver will search each bit position to determine octet alignment.
The 57-octet PLCP framing state machine contains three states: in-frame,
out-of-frame, and loss-of-frame. Valid framing is found when two consecutive
valid path overhead octets in sequence are observed after the A1, A2 framing
octets. The out-of-frame state is entered only from the in-frame state, when there
are errors in both the A1 and A2 octets or when there are two consecutive Pn
errors. This event is an OOF event, and is counted. The LOF state is entered after
eight consecutive PLCP frames in the out-of-frame state.
Stuffing and destuffing are provided according to the PHY type setting in
57-octet formats. Cycle stuffing is used at the transmit PLCP for DS3 and E3
whenever the receive PLCP is in the LOF state or the RCV_HLD input is high,
and this function is enabled with Receiver Hold Enable [bit 10] of CONFIG_1
[0x00]. Cycle stuffing can also be forced by setting Force Cycle Stuffing [bit 6]
of CONFIG_3 [0x02] high.
NOTE: When the framing mode is dynamically modified between direct mapping
and PLCP framing, the CN8223 will go into an OOF state. Dynamic
switching should only be used if necessary.
2.6.4.1 PLCP Status
Errors in either the A1 or A2 PLCP framing octets cause an indication in the
LINE_STATUS register PLCP Frame Error bit and are counted. PLCP OOF
events are indicated by the PLCP OOF bit and counted. PLCP LOF events (OOF
for eight consecutive PLCP frames) are indicated by the PLCP LOF bit. If an
LOF condition persists for more than 2–3 seconds, the PLCP LOF 2–3 status bit
is set. This is determined by LOF being set for three consecutive rising edges of
the ONESECI input. Loss of cell delineation in 53-octet modes is indicated by the
LOC bit and counted. PLCP OOF and LOC indications also appear on the LOCD
output pin.
The PLCP Yellow Alarm status bit is set high after 10 consecutive frames with
a PLCP yellow alarm value of one and cleared after 10 consecutive frames of a
value of zero.
Errors detected in the receiver BIP-8 code checking circuit cause BIP-8 Error
to be set and counted. FEBE Error is set if any valid non-zero FEBE value (values
of 1 through 8) is received. This condition is also counted in the REM_BIP
counter. Invalid FEBE is set if any invalid FEBE value (9 through F) is received; a
value of F also causes FEBE All 1s to be set. This value is used to indicate that
the FEBE calculation is not supported at the far end of the circuit.
100046C
Conexant
2-35
CONEXANT [ CONEXANT SYSTEMS, INC ]
