Bt860/861
6.0 Parametric Data and Specifications
6.1 Electrical Specifications
Multiport YCrCb to NTSC/PAL /SECAM
Figure 6-1. Pixel and Control Data Timing Diagram
System Clock
t
1
t
3
HSYNC*
VSYNC*
BLANK*
OSD[7:0]
P[7:0]
Input
Timing
t
2
t
t
5
4
Output
Timing
HSYNC*
VSYNC*
FIELD
861_038
Table 6-3. AC Characteristics
Parameter
Conditions
Minimum
Typical
27
Maximum
Units
MHz
%
(1)
—
40
3
—
60
12
—
15
—
CLKIN Frequency
CLKIN Pulse Width Duty Cycle
Pixel/Control Setup Time
Pixel/Control Hold Time
t
t
t
t
t
50
1
2
3
4
5
—
ns
0
—
ns
Control Output Delay Time
Control Output Hold Time
—
2
—
ns
—
ns
Power Characteristics
6 DACs enabled
Total current
—
—
—
—
350
250
100
4
—
—
—
—
mA
mA
mA
mA
VAA Supply Current
VDD Supply Current
Sleep Current
6 DACs enabled
—
Using CLKIN as source,
PLL and crystal circuitry
disabled
DAC Current
RSET = 300 Ω,
—
34.13
—
mA
R
= 37.5 Ω
load
PLL Current
—
—
—
—
12
2
—
—
mA
mA
Crystal Circuitry Current
NOTE(S):
(1)
The target frequency is 27 MHz for ITU-R BT.601 timing, 24.5454 MHz for 525 line square pixel timing and 29.5 MHz for 625
line square pixel timing.
D860DSA
Conexant
6-3
CONEXANT [ CONEXANT SYSTEMS, INC ]
