Bt860/861
1.0 Functional Description
1.1 Pin Descriptions
Multiport YCrCb to NTSC/PAL /SECAM
Table 1-1. Pin Assignments (2 of 3)
Pin Name
I/O
Pin #
Description
GRAPHIC AND BLENDING PINS
OSD[7:0]
I
40-39, 36-31
30-29
Dedicated graphic overlay port (TTL compatible.) Accepts pixel data in 8-bit YCrCb
4:2:2 format. Data is latched on the rising edge of the system clock(1) (2)
.
ALPHA[1:0]
I
Alpha blend pins. Provides for 1-, 2-, or 4-bit external blend selection between video
and graphic overlay data. Data is latched on the rising edge of the system clock(1) (2)
.
TELETEXT AND SERIAL CONTROL INTERFACE
TTXDAT
TTXREQ
ALTADDR
I
74
73
62
Teletext data input (TTL compatible)(1)
.
O
Teletext request output (TTL compatible).
I/O
Alternate slave address input (TTL compatible). This pin is sampled immediately
following a power-up or pin reset. A logical 1 corresponds to write address of 0x88
and a read address of 0x89, while a logical 0 corresponds to a write address of 0x8A
and a read address of 0x8B. See Chapter 5.0, for more detail. This pin also provides
special SCART signals when register field SCART_SEL≠00.
SID
SIC
I/O
I
75
76
Serial programming interface data input/output (TTL compatible). Data is written to
and read from the device via this serial bus.
Serial programming interface clock input (TTL compatible). The maximum clock rate is
400 kHz.
ANALOG VIDEO
DACA
DACB
DACC
DACD
DACE
DACF
O
O
O
O
O
O
I
59
58
57
44
43
42
DAC A output. See Table 3-9.
DAC B output. See Table 3-9.
DAC C output. See Table 3-9.
DAC D output. See Table 3-9.
DAC E output. See Table 3-9.
DAC F output. See Table 3-9.
FSADJ1
FSADJ2
53
48
Full-scale adjust control pin. Resistors RSET1 and RSET2 connected between these
pins and AGND control the full-scale output current of the DACs. For standard
operation, use the nominal values shown under Recommended Operating
Conditions. FSADJ1 controls DACs A/B/C and FSADJ2 controls DACs D/E/F.
VREF
O
O
O
49
Voltage reference pin. A 1.0 µF ceramic capacitor must be used to decouple this pin
to AGND. The capacitor must be as close to the device as possible to keep lead
lengths to an absolute minimum.
COMP1
COMP2
54
47
Compensation pin. A 0.1 µF ceramic capacitor must be used to decouple this pin to
VAA. The capacitor must be as close to the device as possible to keep lead lengths
to an absolute minimum.
VBIAS1
VBIAS2
56
45
DAC bias voltage. Use a 0.1 µF ceramic capacitor to bypass this pin to AGND; the
capacitor must be as close to the device as possible to keep lead lengths to an
absolute minimum.
D860DSA
Conexant
1-3
CONEXANT [ CONEXANT SYSTEMS, INC ]
