5.0 Serial Programming Interface and Registers
5.4 Register Detail
Bt860/861
Multiport YCrCb to NTSC/PAL /SECAM
Register 70–71
Default
Value
Register
D7
D6
D5
D4
LC_FIFOWIN[7:0]
Reserved
D3
D2
D1
D0
70
71
80
LC_FIFOWIN[8]
01
Reserved bits should be set to zero when written and will return zero when read.
LC_FIFOWIN[8:0]
FIFO Window
Defines the number of FIFO locations used to accommodate VID port input.
Register 72
Default
Value
Register
D7
D6
D5
D4
D3
D2
D1
D0
72
80
LC_MAXOFF[7:0]
LC_MAXOFF[7:0]
Max Adjustment
Defines the maximum internal PLL adjustment applied when locking is enabled.
Register 73
Default
Register
D7
D6
XL_GAIN[3:0]
Accelerated Locking Gain
D5
D4
D3
D2
D1
D0
Value
73
72
XL_SAT[3:0]
XL_GAIN[3:0]
Defines the gain applied to the detected frequency error to calculate the internal PLL
adjustment for accelerated locking.
XL_SAT[3:0]
Accelerated Locking Saturation
Defines the saturation limit applied to the initial internal PLL adjustment of the
accelerated locking sequence when XL_SATEN is set.
5-38
Conexant
D860DSA
CONEXANT [ CONEXANT SYSTEMS, INC ]
