Bt8370/8375/8376
2.0 Circuit Description
Fully Integrated T1/E1 Framer and Line Interface
2.9 Transmit Line Interface Unit
The TLIU can be used independently of the XMTR by applying P and N rail
NRZ data to the TPOSI and TNEGI pins. Figure 2-34 shows the relationship
between the P and N rail NRZ data, the transmit clock input, and XTIP/XRING.
The transmit clock input can be supplied on the Transmit Clock Input pin (TCKI)
or can be slaved to other clocks in the system using the Clock Input Mux register
[CMUX; addr 01A]. This figure also shows the XTIP/XRING outputs being
three-stated using the XOE pin.
Figure 2-34. TLIU Waveform
LCV
TPOSI
1
3
4
5
7
2
6
8
7
TNEGI
TCKI
Throughput
Delay
5
4
1
3
XTIP, XRING
XOE
6
8
2
LCV
NOTE(S): Transmit jitter attenuation bypassed.
N8370DSE
Conexant
2-69