Bt8370/8375/8376
1.0 Pin Descriptions
1.1 Pin Assignments
Fully Integrated T1/E1 Framer and Line Interface
Table 1-1. Hardware Signal Definitions (8 of 8)
Pin Label
Signal Name
I/O
Definition
Clock Rate Adapter (CLAD)
CLADI
CLAD Input
I
I
Optional CLAD input timing reference used to phase lock CLADO and JCLK
outputs to 1 of 44 different input clock frequencies selected in the range of
8 kHz to 16384 kHz (see [CLAD registers; addr 090–092]).
REFCKI
CLADO
Reference Clock
System must apply a 10 MHz ±50 ppm clock signal to act as frequency
reference for internal Numerical Controlled Oscillator (NCO). REFCKI
determines frequency accuracy and stability of CLADO and jitter attenuator
(JCLK) clocks when the NCO operates in free running mode (see [JFREE;
addr 002]).
REFCKI is the baseband reference for all CLAD/JAT functions and is used
internally to generate clocks of various frequencies, locked to a selected
receive, transmit, or external clock. Hence, REFCKI is always required.
CLAD Output
O
CLADO is configured to operate at 1 of 14 different clock frequencies (see
[CSEL; addr 091]) that include T1, E1 or system bus rates. CLADO is
typically programmed to supply RSB and TSB clocks that are
phase-locked to the selected transmit, receive or CLADI timing reference
(see [JEN; addr 002 and CEN; addr 090]). On the Bt8376 device, CLAD0
drives low when enabled.
Test Access
TDI
JTAG Test Data Input
I
I
Test data input per IEEE Std 1149.1-1990. Used for loading all serial
instructions and data into internal test logic. Sampled on the rising edge of
TCK. TDI can be left unconnected if it is not being used because it is pulled
up internally.
TMS
JTAG Test mode
Select
Active-low test mode select input per IEEE Std 1149.1-1990. Internally
pulled-up input signal used to control the test-logic state machine.
Sampled on the rising edge of TCK. TMS can be left unconnected if it is
not being used because it is pulled up internally.
TDO
TCK
JTAG Test Data
Output
O
I
Test data output per IEEE Std 1149.1-1990. Three-state output used for
reading all serial configuration and test data from internal test logic.
Updated on the falling edge of TCK.
JTAG Test Clock
Test clock input per IEEE Std 1149.1-1990. Used for all test interface and
internal test-logic operations. If unused, TCK must be pulled low.
Power Supply
VDD[6:0]
GND[6:0]
NOTE(S):
Power
I
I
+5 VDC ±5%
Ground
0 VDC
1. I = Input, O = Output
2. PIO = Programmable I/O; controls located at address 018.
3. Multiple signal names show mutually exclusive pin functions.
4. All output pins power up in the high-impedance state within 3,000 cycles of the applied REFCKI (see POE; addr 019,
SBI_OE; addr 0D0).
N8370DSE
Conexant
1-11
CONEXANT [ CONEXANT SYSTEMS, INC ]
