Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
3.16 Data Link Registers
must read from RDL2 after RNEAR interrupt to clear the RNEAR2 indicator, and how much
time remains (in bytes) for the processor to read RDL2 before receive FIFO is full. If a receive
message is in progress when the near full threshold is reached, the receiver issues a message
interrupt [RMSG; addr 00A] and places a Partial message in the receive FIFO.
FFC[5:0]
00 0000
00 0001
00 0010
|
Empty @ RNEAR
none
Filled @ RNEAR
64 = RFULL
63 filled
1 empty FIFO location
2 empty FIFO locations
|
62 filled
|
11 1110
11 1111
62 empty FIFO locations
63 empty FIFO locations
1 filled
0 filled = empty
N8370DSE
Conexant
3-105