Bt8370/8375/8376
Fully Integrated T1/E1 Framer and Line Interface
3.12 Transmitter Registers
3
3.12 Transmitter Registers
Unused bits indicated by a dash (—) are reserved and should be written to 0. Writing to reserved bits has no
effect.
070—Transmit Framer Configuration (TCR0)
TCR0 selects the offline framer's criteria for recovery of transmit frame alignment; it determines the output of
transmit frame and alarm formatters overhead bits, and works in conjunction with TCR1 [addr 071] and TFRM
[addr 072]. This allows TCR0 to select the transmit online frame monitor's criteria for loss of frame alignment,
and which overhead bits are supplied by the transmit frame and the alarm formatters.
7
6
5
4
3
2
1
0
—
—
—
—
TFRAME[3]
TFRAME[2]
TFRAME[1]
TFRAME[0]
TFRAME[3:0]
The frame formatter generates Ft, Fs, FPS, FAS, MFAS, and CRC bits. The alarm formatter
generates YB2, YJ, Y0, and Y16 bits. Frame and alarm overhead formats are selected by
TFRAME[3:0] and T1/E1N settings, as listed in Tables 3-15 through 3-18. Each Yellow Alarm
can be generated manually or automatically [TALM; addr 075], or can be bypassed
[INS_MYEL; addr 072].
The frame formatter does not generate CAS or Sa-bit overhead; these bits are supplied by
TPCMI in Bypass mode [TFRM; addr 072], or by programming TSIGn [addr 120–13F] or
TSA4–TSA8 [addr 07B–07F] buffer contents. To insert CAS, the processor selects TLOCAL
output signaling for time slot 0 and time slot 16 by programming transmit per-channel control
registers TPC0 [addr 100] and TPC16 [addr 110]. The processor then fills ABCD local
signaling value for TPC0 with the MAS pattern (ABCD = 0000) and TPC16 with XYXX
pattern (ABCD = 1011).
The frame formatter does not generate SLC, T1DM, or FDL overhead; these bits are
supplied either by TPCMI in Bypass mode [TFRM; addr 072] or by programming the TSLIP
[addr 140–17F], TDL1 [addr 0AD], or TDL2 [addr 0B8] buffer contents.
To insert SLC concentrator, maintenance, alarm, and switch field values, the processor
selects any SLC framer format and programs either the TDL1 or the TDL2 to operate in
unformatted Pack6 mode over the F-bit channel during even frames. This overwrites all Fs bits
inserted by the frame formatter. The data pattern to be sent in 36 Fs bit multiframe is written as
six 6-bit words to the TDL1 or TDL2 circular buffer. For real-time overhead manipulation, the
processor can rewrite the circular buffer with a new 36-bit pattern, as desired.
To insert T1DM, the processor enables TIDLE insertion on time slot 24 by programming
the transmit per-channel control [TDC24; addr 118], and filling the TSLIP buffer location for
TS24 [addr 158] with the T1DM framing pattern (TS24 = 10111YR0). If specific T1DM
elements must be inserted and others bypassed, the processor configures TDL1 or TDL2 to
selectively insert only the desired bits such as the T1DM sync pattern, R-bits, and/or Y-bits, by
programming data link bit enables [DL1_BIT; addr 0A5 or DL2_BIT; addr 0B0].
To insert FDL, the processor configures TDL1 to operate over the F-bit channel during odd
frames [DL1_TS; addr 0A4] and during Automatic Performance Report Messages
[AUTO_PRM; addr 0AA], or the processor manually programs TDL1 to send each message.
N8370DSE
Conexant
3-67
CONEXANT [ CONEXANT SYSTEMS, INC ]
