AccessRunner
Controller-less ADSL Modem Device Set for PCI Applications
Pin Name
I/O1
Description
AFE_WAKEUP
SERIAL EEPROM
EEPROM_CS
I (S)
DSL Power Management Wakeup Signal from AFE
O
O
I
EEPROM Chip Select
EEPROM Clock
EEPROM_CLK
EEPROM_DIN
EEPROM Data Input
EEPROM Data Output
EEPROM_DOUT
PCI POWER MANAGEMENT
PCI_VAUXDET
PCI_VPCIDET
O
I (PD,S)
Vaux Detect
Vpci Detect
Vaux Enable
Vpci Enable
I (PD,S)
PCI_VAUXEN#
PCI_VPCIEN#
O
O
I
PCI_VPCIPREFER
This pin is used to determine whether Vpci or Vaux is the preferred power supply.
1=Vpci preferred, 0=Vaux preferred
MISCELLANEOUS
GPIO[1:0]
I/O (PU,S)
I/O (PU)
I/O
General Purpose Schmitt Input/Output
GPIO[2:5], GPIO[8]
GPIO[6]
General Purpose Input/Output
General Purpose Input/Output (also used for active low reset)
General Purpose Input/Output (also used for active high reset)
GPIO[7]
I/O
TDI_GPIO[9]
I/O (PU)
JTAG test data input OR general purpose input/output. Function of this pin is
dependant upon value of JTAGEN bit. When operating in JTAG mode this signal
contains serial data that is shifted in on the rising edge of TCK.
TMS_GPIO[10]
I/O (PU)
I/O (PU)
JTAG test mode select OR general purpose input/output.
Function of this pin is dependant upon value of JTAGEN bit. When operating in JTAG
mode this siganl controls the operation of the TAP controller.
TRSTN_GPIO[11]
JTAG reset OR general purpose input/output.
Function of this pin is dependant upon value of JTAGEN bit. When operating in JTAG
mode, a high to low transition on this signal forces the TAP controller into a logic reset
state.
TCK
TDO
I
JTAG clock.
O
JTAG data output. This pin generates serial data that is shifted out on the falling edge
of TCK..
GPIN0
I (S)
General purpose schmitt input (modem ring detect)
GPIN1
I (PU,S)
I (PD)
I (PD)
I
General purpose schmitt input (modem offhook)
SCANEN
SCANMODE
REFCLK
POWER AND GROUND
VDD
Scan chain enable. Used to shift data in and out of the scan chain.
Scan mode enable pin. When tied high it will put the device into scan test mode.
35.328 MHz reference clock used to create the internal 53 MHz system clock
3.3V Power
Ground
GND
VGG1
I/O Clamp Power Supply for PCI Signalling Environment (connect to VIO pin of PCI
Bus)
VGG2
I/O Clamp Power Supply for Backend (connect to 3.3 volt supply)
8
Conexant
Proprietary Information
Doc. No. 100394B
October 19, 1999
CONEXANT [ CONEXANT SYSTEMS, INC ]
