4.0 Electrical and Mechanical Specifications
CN8223
4.3 Timing
ATM Transmitter/Receiver with UTOPIA Interface
4.3 Timing
This section includes timing diagrams and descriptions for the CN8223.
4.3.1 Microprocessor Interface Timing
Table 4-2 and Figure 4-1 display the timing requirements and characteristics of
the microprocessor interface. All times are in nanoseconds.
Table 4-2. Microprocessor Interface Timing
Name Description
t
Min
30
10
10
4
Max
Processor Clock Period
2X Cell Rate
prclk
t
Processor Clock Pulse Width High
—
—
—
—
—
—
—
prh
t
Processor Clock Pulse Width Low
prl
t
Address Strobe Setup to Processor Clock Rising Edge
Address Setup to Processor Clock Rising Edge
Chip Select Setup to Processor Clock Rising Edge
Chip Select to Processor Clock Rising Edge Hold Time
Write/Read Control Setup to Processor Clock Rising Edge
Address Strobe Hold after Processor Clock Rising Edge
Data Setup to Processor Clock Rising Edge (write cycle)
Data Hold after Processor Clock Rising Edge (write cycle)
Output Enable Low to Data Bus Driven (read cycle)
Output Enable Low to Data Bus Valid (read cycle)
Output Enable High to Data Bus Invalid (read cycle)
Output Enable High to Data Bus High-Z (read cycle)
PRCLK High to Data Bus Driven (read cycle, OE~ low)
PRCLK High to Data Bus Valid (read cycle, OE~ low)
PRCLK high to Data Bus Invalid (read cycle, OE~ low)
PRCLK High to Data Bus High-Z (read cycle, OE~ low)
aspr
t
1
apr
t
4
cspr
t
8
csph
t
1
wpr
t
t
+ 2 ns
t
prl
– 4 ns
—
pras
prh
t
1.0
3.0
1.5
1.6
1.3
1.4
3.5
3.6
3.2
3.2
dpr
prd
t
—
t
6.0
odd
t
t
6.0
odv
t
4.9
odi
odz
pdd
5.1
t
11.0
11.0
10.0
10.0
t
pdv
t
pdi
t
pdz
4-4
Conexant
100046C
CONEXANT [ CONEXANT SYSTEMS, INC ]
