1.0 Product Description
CN8223
1.1 Block Diagram
ATM Transmitter/Receiver with UTOPIA Interface
Figure 1-1. CN8223 Detailed Block Diagram
PRCLK
CS~
AS~
W/R~
OE~
TMRKR
TOVH_CLK TXOVH
DL_INT
STAT_INT
A[7:1] D[15:0] SEL8BIT
8
16
8
Cell Counters
Performance
Monitoring
TCLKO_HS
TXOUT_HS
TXCKI_HS
RXCKI_HS
RXIN_HS
Line
Microprocessor
Interface
Interfaces
Tx
Overhead
Insert
Tx
HDLC
Tx
FEAC
Interrupt Control
High
Speed
Port 0 Ctrl
Port 1 Ctrl
Port 2 Ctrl
DS3, E3, E4, STS-1
STS-3c, STM-1
G.832
Tx Cell
Transmit G.832
and PLCP
Framer
4-Port
FIFO
Generation,
Tx Rate
TCLKO
TXOUT
TXCKI
RXCKI
Medium
Speed
FCTRL_OUT[16:0]
FCTRL_IN[7:0]
Data
Transmit Framer
and Priority
Interface
Port 3 Ctrl
RXIN
RCV_HLD
LOCD
UTOPIA
Interface
and
UTOPIA Ctrl
Rx Cell
Validation
Rx VPI/VCI
Screening
DS3, E3, E4, STS-1
STS-3c, STM-1
G.832
Receive G.832
and PLCP
Framer
4-Cell
9
Buffers
Parallel
Interface
Receive Framer
TXOUT[7:0]
RXIN[7:0]
FDAT_IN
FDAT_OUT
9
9
9
Rx
Overhead
Extract
Rx
HDLC
Rx
FEAC
Clock and
Control
CN8223
8
RMRKR RXOVH
ROVH_CLK
ONESECI ONESECO
8KCKI
NTEST
TEST1, 3
RESET
Line Framer Section
Cell Processing
FIFO Data Ports Section
Section
1-2
Conexant
100046C
CONEXANT [ CONEXANT SYSTEMS, INC ]
