4-Level FSK Modem Data Pump
Page 34 of 50
MX929B PRELIMINARY INFORMATION
START
Ensure that the Control Register
has been loaded with
Set µC variable 'IBLOCKS'
to the number of Intermediate blocks
to be transmitted
a suitable CKDIV value
Ensure that the Mode Register
IRQEN, PSAVE, RXEYE and SSIEN bits are '0',
the TX/RX bit is '1'
Set µC variable 'STATE' to 0
Set the Mode Register IRQEN bit to '1'
Enable µC's MX929B Tx Interrupt Service Routine
and the INVSYM and SSYM bits are
set appropriately
Write a RESET task to the Command Register
Read the Status Register
Write 6 bytes of Symbol Sync
pattern to the Data Buffer
Yes
BFREE bit = 1 ?
Write a T24S task to the Command Register
No
Note: during this time the µC may
perform other functions, as the
µC variable 'STATE' is updated
by the interrupt service routine
'STATE' < 6 ?
Yes
No
Disable µC's MX929B Tx Interrupt Service Routine
Set the Mode Register IRQEN bit to '0'
No
'STATE' = 6 ?
Yes
END
with error
END
Figure 19: Transmit Frame Example Flowchart, Main Program
Notes:
1. The RESET command in Figure 19 and the practice of disabling the MX929B’s IRQ output when not
needed are not essential but can eliminate problems during debugging and if errors occur in operation
2. The CRC and TXIMP bits should be set appropriately every time a byte is written to the Command
Register.
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