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MX839 参数 Datasheet PDF下载

MX839图片预览
型号: MX839
PDF下载: 下载PDF文件 查看货源
内容描述: 数字控制的模拟I / O处理器 [Digitally Controlled Analog I/O Processor]
分类和应用:
文件页数/大小: 20 页 / 169 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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Digitally Controlled Analog I/O Processor  
8
MX839 PRELIMINARY INFORMATION  
4.5.2 Write Only Register (8-Bit and 16-Bit)  
HEX  
ADDRESS/  
COMMAN  
D
REGISTER  
NAME  
BIT 7  
(D7)  
BIT 6  
(D6)  
BIT 5  
(D5)  
BIT 4  
(D4)  
BIT 3  
(D3)  
BIT 2  
(D2)  
BIT 1  
(D1)  
BIT 0  
(D0)  
$01  
$D0  
$D2  
RESET  
CLOCK  
N/A  
0
N/A  
0
N/A  
N/A  
0
N/A  
0
N/A  
N/A  
N/A  
BIT 0  
BIT 0  
BIT 0  
0
DIVIDER  
BIT 1  
CONTROL  
VARIABLE  
ATTENUATOR (1)  
VARIABLE  
ATTENUATOR (2)  
DAC  
0
BIT 2  
MOD1  
BIT 2  
MOD2  
BIT 2  
DAC2  
MOD1  
ENABLE  
MOD2  
ENABLE  
NBIT  
0
0
BIT 4  
BIT 4  
0
BIT 3  
BIT 1  
0
0
BIT 3  
BIT 1  
NBIT  
DAC1  
NBIT  
DAC2  
DAC1  
DAC3  
$D3  
$D4  
CONTROL  
DAC1 DATA  
(1)  
DAC3  
ENABLE ENABLE ENABLE  
BIT 7  
BIT 6  
BIT 5  
0
BIT 4  
0
BIT 3  
0
BIT 2  
0
BIT 1  
BIT 9  
BIT 1  
BIT 9  
BIT 1  
BIT 0  
BIT 8  
BIT 0  
BIT 8  
BIT 0  
BIT 8  
0
*See Note 1  
(2)  
0
BIT 7  
0
0
BIT 6  
0
DAC2 DATA  
(1)  
$D5  
$D6  
BIT 5  
0
BIT 4  
0
BIT 3  
0
BIT 2  
0
*See Note 1  
(2)  
DAC3 DATA  
(1)  
BIT 7  
0
BIT 6  
0
BIT 5  
0
BIT 4  
BIT 3  
BIT 2  
*See Note 1  
(2)  
0
0
0
BIT 9  
A/DIN4  
ACTIVE  
A/D  
A/DIN1  
ACTIVE  
A/DIN2  
ACTIVE  
A/DIN3  
ACTIVE  
$D7  
$D8  
CONTROL  
0
1
READ  
MAG COMP ONE  
LEVELS (1)  
MAGNITUDE COMPARATOR UPPER LEVEL  
BIT 5 BIT 4 BIT 3 BIT 2  
MAGNITUDE COMPARATOR LOWER LEVEL  
BIT 5 BIT 4 BIT 3 BIT 2  
MAGNITUDE COMPARATOR UPPER LEVEL  
BIT 5 BIT 4 BIT 3 BIT 2  
MAGNITUDE COMPARATOR LOWER LEVEL  
BIT 5 BIT 4 BIT 3 BIT 2  
MAGNITUDE COMPARATOR UPPER LEVEL  
BIT 5 BIT 4 BIT 3 BIT 2  
MAGNITUDE COMPARATOR LOWER LEVEL  
BIT 5 BIT 4 BIT 3 BIT 2  
MAGNITUDE COMPARATOR UPPER LEVEL  
BIT 5 BIT 4 BIT 3 BIT 2  
MAGNITUDE COMPARATOR LOWER LEVEL  
BIT 5 BIT 4 BIT 3 BIT 2  
BIT 7  
BIT 7  
BIT 7  
BIT 7  
BIT 7  
BIT 7  
BIT 7  
BIT 7  
BIT 6  
BIT 6  
BIT 6  
BIT 6  
BIT 6  
BIT 6  
BIT 6  
BIT 6  
BIT 1  
BIT 1  
BIT 1  
BIT 1  
BIT 1  
BIT 1  
BIT 1  
BIT 1  
BIT 0  
BIT 0  
BIT 0  
BIT 0  
BIT 0  
BIT 0  
BIT 0  
BIT 0  
MAG COMP ONE  
LEVELS (2)  
MAG COMP TWO  
LEVELS (1)  
$D9  
$DA  
$DB  
MAG COMP TWO  
LEVELS (2)  
MAG COMP THREE  
LEVELS (1)  
MAG COMP THREE  
LEVELS (2)  
MAG COMP FOUR  
LEVELS (1)  
MAG COMP FOUR  
LEVELS (2)  
Table 2: Write Only Register (8-Bit and 16-Bit)  
Note  
1. A second byte is expected by the 'C-BUS' interface only when the 'NBIT DACn' bit of the 'DAC Control Register' is  
set high. Otherwise, the data transfer is a single byte (Bit 7 to Bit 0).  
© 1998 MXxCOM Inc.  
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054  
Doc. # 20480164.002  
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA  
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