MSK Modem
9
MX809
5.3 Write to Control Register
This “Write Only” register directs the Modem’s operation.
SYNC: When set, this bit enables SYNC Word detection. It is cleared on a successful SYNC Word
detection.
SYNC Prime: When set, this bit enables SYNC Word detection. It is cleared on a successful SYNC Word
detection.
Interrupt Enable: When set, this bit allows interrupts to be output by the MX809 on the IRQ line.
Powersave: Used in conjunction with the Wake input (see Section 2) to control the Powersave state of the
MX809.
Checksum Enable: When set:
In TX: A 2-byte checksum is generated and transmitted after every 6 bytes transmitted.
In RX: After every 8 received bytes (6 information + 2 checksum) the checksum word is checked. If
the checksum is correct, the RX Checksum True bit in the Status Register is set to a logic “1”. When
this bit is a logic “0” no checksum are generated or checked.
Note: Checksum operation is inhibited during the SYNC/SYNC search period.
Setting
MSB
Control bits
Transmitter first
Not Used
Bit 7
Set to “0”
6
Not Used
Set to “0”
5
SYNC Prime
0
1
Primed
4
SYNC Prime
0
1
Primed
3
Interrupt Enable
0
1
Disable
Enable
2
Powersave
0
1
Normal Operation
Powersave
1
Checksum Enable
0
1
Disable
Enable
0
RX/TX Mode
0
1
RX
TX
Table 7: Control Register
5.4 RX Data buffer -- “Read RX Data Buffer”
This “Read Only” register contains the last byte of data received from the Data Register. Data is received Bit
7 (MSB) first.
MSB
LSB
7
6
5
4
3
2
1
0
RX Data Buffer
ꢀ1998 MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480036.004
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CMLMICRO [ CML MICROCIRCUITS ]
