MSK Modem
10
MX809
5.5 TX Data Buffer -- “Write to TX Data Buffer”
This “Write Only” register contains the next byte of data to be transmitted. Bit 7 (MSB) is transmitted first.
MSB
LSB
7
6
5
4
3
2
1
0
TX Data Buffer
5.6 SYNC Program -- “Write to SYNC Program”
This “Write Only” register is loaded with the required SYNC word. This word (or its opposite logic sense,
SYNC ) is compared with the received synchronization word. If the required SYNC Word is less that 16bits,
the remaining bits must be programmed as preamble (10101010…etc). Bit 15 (MSB) is loaded first.
Byte 1
Byte 2
MSB
LSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SYNC High
SYNC Low
5.7 Read Status Register
This “Read Only” register indicated the source of MX809 interrupts (IRQs ).
RX SYNC Detect: This is set and an Interrupt is generated when the correct SYNC Word is detected (if
SYNC Prime is set).
It is cleared by (1) reading the Status Register, and (2) setting RX/ TX to logic “1”.
RX SYNC Detect: This is set and an Interrupt is generated when the correct SYNC Word is detected (if
SYNC Prime is set).
It is cleared by (1) reading the Status Register, and (2) setting RX/ TX to logic “1”.
TX Idle: This is set and an Interrupt is generated when all loaded TX data and 1 “hang-bit” have been
transmitted.
It is cleared by (1) writing to the TX Data Buffer, and (2) setting RX/ TX to logic “0”.
TX Data Ready: This is set and an Interrupt generated indicating that a byte of data should be written to the
TX Data Buffer.
It is cleared by (1) reading the Status Register and writing a byte of data to the TX Data Buffer, and (2) setting
RX/ TX to logic “0”.
RX Data Ready: When this is set and an Interrupt generated, it indicates that the RX Data Buffer is full, and
that a byte of data is to be read from the RX Data buffer. This must be read within 8 bit periods.
It is cleared by (1) reading the Status Register and the RX Data buffer, and (2) setting the RX/ TX to logic “1”/
RX Checksum True: This is set and an Interrupt is generated by a successful comparison of the received
and self-generated checksums.
It is cleared by (1) reading the Status Register and the RX Data Buffer, and (2) RX/ TX being taken to logic
“1”
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