MSK Modem
11
MX809
Reading
MSB
Status Bits
Received First
Undefined
Bit 7
0
1
“0” or
“1”
6
Undefined
0
1
“0” or
“1”
5
RX SYNC Detect
0
1
SYNC
4
RX SYNC Detect
0
1
SYNC
3
TX Idle
0
1
Idle
2
TX Data Ready
0
1
TX Date Ready
1
RX Checksum True
0
1
True
0
RX Data Ready
0
1
RX Data Ready
Table 8: Status Register
5.8 Interrupt Request
The conditions that cause interrupts to be output (if enabled by the Control Register) from the MX809 are:
TX Idle
TX Data Ready
RX SYNC Detect
RX Data Ready
RX SYNC Detect
The Status Register should be read to find the cause of the interrupt. Interrupts are cleared by (1) reading the
Status Register, or (2) changing the state of the RX / TX bit.
5.9 General Reset
Upon power-up, the bits in the MX809 Mode register and buffer will be random (either “0” or “1”). The
General Reset command (01 ) will “reset” all microcircuits in the C-BUS and had the following effect on the
H
MX809.
All bits in the Control Register will be set to logic “0”. The Tx Out output will be set to V
.
BIAS
Note: The Status register, RX Data Buffer, TX Data Buffer, and SYNC Program register are not affected by
the General Reset Command.
ꢀ1998 MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480036.004
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