Audio Processor
21
MX806A
7.1.4 Timing
Timing Parameters for two-way communications between the ꢃC and the MX805A on the C-BUS are shown
in Table 12.
C-BUS Timing
Min.
2.0
4.0
2.0
4.0
2.0
Typ. Max. Units
t
t
t
t
t
Chip Select Low to First Serial Clock Rising Edge
ꢃs
ꢃs
ꢃs
ꢃs
ꢃs
CSE
CHS
CSOFF
NXT
CK
Last Serial Clock Rising Edge to Chip Select High
Chip Select High time between transactions
Inter-Byte Time
Serial Clock Period
Table 12: Timing Information
Notes:
1. Command Data is transmitted to the peripheral MSB (bit 7) first, LSB (bit 0) last. Reply Data is read from
the MX805A MXB (bit 7) first, LSB (bit 0) last.
2. Data is clocked into the MX805A and into the microcontroller on the rising Serial Clock edge.
3. Loaded data instructions are acted upon at the end of each individual, loaded byte.
4. To allow for differing microcontroller serial interface formats, the MX806A will work with either polarity
Serial Clock pulses.
tCSOFF
CHIP SELECT
tCSE
tCSH
tNXT
tNXT
SERIAL CLOCK
tCK
COMMAND DATA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
LSB
FIRST DATA BYTE
LAST DATA BYTE
ADDRESS/COMMAND
BYTE
Logic level is not important
Figure 7: C-BUS Timing Information
ꢀ1998 MX-COM, Inc.
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