Sub-Audio Signaling Processor
Page 12 of 24
MX805A
5.2.1 Write to Control Register - A/C 70H (78H) followed by 1 byte of Command Data
Table 6 shows the configurations available to the MX805A. Bits 5, 6, and 7 are used together to Enable and
Powersave circuits sections as required.
Setting
6
Control Bits
Powersaved
Transmitted First
Enabled
MSB
7
5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CTCSS Decoder
NRZ Decoder and Both Encoders
CTCSS Decoder and Both Encoders
All Decoders
NRZ Decoder
CTCSS Encoder
NRZ Encoder
All Decoders
CTCSS Encoder and Decoder
NRZ Encoder and CTCSS Decoder
NRZ Decoder and CTCSS Decoder
NRZ Decoder
NRZ Encoder and Decoder
No circuits
All Encoders
All Encodes except Tx Sub-Audio LPF
and CTCSS Decoder
4
1
Enable Audio Output – Used with Bit 3
0
Disable Audio Output – output to V
BIAS
3
1
Enable Sub-Audio Bandstop Filter (Audio Signal Path)
Bypass Sub-Audio Bandstop Filter
0
2
1
Enable All MX805A Interrupts
Disable All MX805A Interrupts
0
1
1
Set Rx Lowpass Filter Bandwidth to 180Hz – for low CTCSS tones or NRZ Data
Set Rx Lowpass Filter Bandwidth to 260Hz
0
0
1
All encoders and Decoders Powersaved
0
All Encoders and Decoders Enabled unless individually Powersaved
Table 6: Control Register
5.2.2 General Reset
Upon power-up the bits in the MX805A registers will be random (either 0 or 1). A General Reset Command
(01 ) will be required to reset all devices on the C-BUS. It has the following effect on the MX805A:
H
Control Register
Status Register
NoTone Timer
Set to 00
Set to 00
Discharged
H
H
Warning: The following MX805A register configurations are not affected by a General Rest Command:
CTCSS Rx Frequency
CTCSS Tx Frequency/NRZ Baud Rate Register
NRZ Rx Data Register
NRZ Tx Data Register
Gain Set Register
Note: Setting the Control Register in this way will set the MX805A to the CTCSS decode mode and overwrite
a “Powersave All” instruction. It should also be considered that a General Reset command will reset All
DBS800 ICs operating on the C-BUS.
ã2001 MX-COM, Inc.
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Doc. # 20480116.006
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