Audio Signaling Processor
Page 11 of 26
MX803A PRELIMINARY INFORMATION
5.2.2 Read Status Register
A/C 31H, followed by 1 byte of Reply Data
Interrupt Requests (IRQ): Interrupts on this device are available to draw the attention of the µC to a change
in the condition of the bit in the status register. However, bits are set in the status register irrespective of the
setting of interrupt enable bits (Table 4) and these changes may be recognized by polling the register.
General Purpose Timer Period: Set to a logic “1” when the timer period has expired. Cleared to a logic “0”
by:
1. Reading the Status Register
2. New G/Purpose Timer information
3. General Reset command
Notone Timer Period: Set to a logic “1” when the timer period has expired. Cleared to a logic “0” by:
1. Reading the Status Register
2. New Notone Timer information
3. General Reset command
RX Tone Measurement: Set to a logic “1” when the RX Tone Measurement is complete. Cleared to a logic
“0” by:
1. Reading the Status Register
2. General Reset command
Setting
MSB
Bit 7
0
Status Bits
Received First
Set to
0
Bit 6
0
Set to
0
Bit 5
0
Set to
0
Bit 4
0
Set to
0
Bit 3
1
Logic Input Status
1
0
0
Bit 2
1
G/Purpose Timer Period
Expired
(Interrupt Generated)
Notone Timer Period
Expired
Bit 1
1
(Interrupt Generated)
RX Tone Measurement
Complete
Bit 0
1
(Interrupt Generated)
Table 5: Status Register
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