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MX802LH 参数 Datasheet PDF下载

MX802LH图片预览
型号: MX802LH
PDF下载: 下载PDF文件 查看货源
内容描述: DVSR CODEC [DVSR CODEC]
分类和应用:
文件页数/大小: 24 页 / 220 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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DVSR CODEC  
11  
MX802  
4.1.4.3 Write Data  
4.1.4.3.1 66 WRITE DATA -- START PAGE “P”  
H
This command sets the Data Write Counter to “P” page, and then writes data bytes to successive DRAM  
locations, incrementing the Data Write Counter by 1 for each bit received via the C-BUS.  
The Start Page, “P,” is indicated by loading a 2-byte word after the relevant Address/Command byte. This 16-  
bit word allows data page addresses from 0 to 65535 (4Mbits DRAM).  
4.1.4.3.2 68 WRITE DATA CONTINUE  
H
This command writes data bytes to successive DRAM locations determined by the Data Write Counter,  
incrementing the counter by 1 for each bit received over the C-BUS.  
4.1.4.4 DRAM Speech Capacity  
28-pin/lead versions of the MX802 may be used with a single 256kbit DRAM, or with up to 4 x 1Mbit of  
DRAM. 24-pin/lead versions may only be used with a single 256kbit or 1Mbit DRAM. The different encode  
and decode sampling clock rates available enable the user to set voice store and play times against  
recovered speech quality. Table 4 gives information on storage capacity and Store/Playback times. Speech  
data can be replayed at a different sample rate or in a reversed sequence (see Control Register for details).  
DRAM Size Available bits Speech Pages  
Nominal Sample Rates (kbps)  
16  
25  
32  
50  
64  
256kbps  
1024kbps  
2Mbps  
262144  
256  
16.0  
65.0  
131.0  
196.0  
262.0  
10.0  
42.0  
84.0  
126.0  
168.0  
8.0  
5.0  
4.0  
1048576  
2097152  
3145738  
4194304  
1024  
2048  
3072  
4096  
32.0  
65.0  
98.0  
131.0  
20.0  
42.0  
63.0  
84.0  
16.0  
32.0  
49.0  
65.5  
3Mbps  
4Mbps  
Table 4: Sampling Clock Rates vs. Speech Storage/Playback Times  
4.1.4.5 Encoder and Decoder Sampling Clocks  
Encoder and decoder sampling clock rates are programmable via the Control Register. Table 5 shows the  
range of sampling rates available for different Xtal/clock input frequencies and the counter ratios used to  
produce them. Consideration should be given to the effect of different Xtal/clock frequencies upon the audio  
frequency performance of the device.  
Control Register  
Byte 0, Bits  
Internal Counter  
Division Ratio  
Xtal Clock Frequency (MHz)  
5
2
0
1
1
1
1
4
1
1
0
0
1
1
3
0
1
0
1
0
1
Dec.  
Enc.  
4.0  
4.032  
4.096  
256  
160  
128  
80  
15.625  
25.0  
15.75  
25.20  
31.50  
50.4  
16.0  
25.60  
32.0  
31.25  
50.0  
51.20  
64.0  
64  
62.50  
63.0  
Table 5: Sampling Clock Rates Available  
With respect to using a single Xtal/clock frequency for all DBS 800 devices in use, it should be noted that  
a. A 4.032MHz Xtal/clock input will produce an accurate 1200-baud rate for the MX809 MSK Modem.  
b. A 4.096MHz Xtal/clock input will generate exactly 16kbps, 32kbps and 64kbps Codec sampling clock  
rates.  
1998 MX-COM, Inc.  
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054  
Doc. # 20480033.008  
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA  
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