Low Voltage SPM Detector
2
MX631
Pin Func tion
1
Xtal/Clock : The input to the on-chip clock oscillator; for use with a 3.579545MHz Xtal in
conjunction with the Xtal output (see Figure 2). Circuit components are on-chip. Using this mode of
clock operation, the Clock Out pin should be connected directly to the Clock In pin. If a clock pulse
input is employed to the Clock In pin, this pin must be connected directly to VDD (see Figure 2).
2
3
Xtal: The output of the on-chip clock oscillator inverter.
Clock Out: The buffered output of the on-chip clock oscillator inverter. If a Xtal input is employed
this output should be connected directly to the Clock In pin.
4
Clock In: The 3.579545MHz clock pulse input to the internal clock-dividers. In the clock pulse input
mode the Xtal/Clock input (pin 1) should be connected to VDD. (See Figure 2.)
5
6
7
No internal connection, leave open circuit.
No internal connection, leave open circuit.
VBIAS: The output of the on-chip analog bias circuitry. Held internally at VDD/2, this pin should be
decoupled to VSS (see Figure 2).
8
VSS: Negative supply (GND).
9
Signal In (+):
Signal In (-):
Amp Out:
The positive and negative inputs to, and the output from,
the input gain adjusting signal amplifier. Refer to Figure 4
for guidance on setting level sensitivities to national specifications,
and the selection of gain adjusting components.
10
11
12
No internal connection, leave open circuit.
13
Tone Follower Output: This output provides a logic “0” (Low) for the period of a detected tone and
a logic “1” (High) for NOTONE detection. See Figure 5.
14
Packet Mode Output: A logic output that will be available after a cumulation of 40ms of 'good' tone
has been received. This packet tone follower will only respond when a tone frequency of sufficient
quality has been received for sufficient time, i.e. a cumulation of 40ms in any 48ms; short tone
bursts or breaks will be ignored. This output provides a logic “0” (Low) for a detected tone and a
logic “1” (High) for NOTONE detection. See Figure 6.
15
16
System: The logic input to select device operation to either 12kHz (logic “1” - High) or 16kHz (logic
“0” - Low) SPM systems. This input has an internal 1MΩ pullup resistor (12kHz).
VDD: Positive supply. A single, stable power supply is required. Critical levels and voltages within the
MX631 are dependent upon this supply. This pin should be decoupled to VSS by a capacitor mounted
close to the pin.
Note that if this device is ‘line’ powered, the resulting supply must be stable. See notes on IC
Protection from high and spurious line voltages.
© 1997 MX•COM, INC.
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