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MX629LH 参数 Datasheet PDF下载

MX629LH图片预览
型号: MX629LH
PDF下载: 下载PDF文件 查看货源
内容描述: [CVSD Codec, CVSD, 1-Func, CMOS, PQCC24, LCC-24]
分类和应用: 电信电信集成电路
文件页数/大小: 16 页 / 357 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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Delta Modulation CODEC  
5
MX629  
J/P LH  
Name  
22 Clock Mode 2  
23 Clock Mode 1  
Signal  
Description  
20  
21  
Clock rates refer to f = 1024MHz Xtal/Clock input. During internal  
operation the data clock frequencies are available at the ports for  
external circuit synchronization. Independent or common data  
rate inputs to Encode and Decode data clock ports may be  
employed in the External Clocks mode. Internal 1Mpullups.  
See Table 3.  
22  
24  
V
DD  
power Positive Supply. A single 5.0V supply is required.  
Table 1: Signal List  
Data Enable  
Powersave  
Encoder Output  
Enable  
High Z (open circuit)  
1
1
0
1
1
0
V
SS  
Table 2: Encoder Output  
Clock Mode 1  
Clock Mode 2  
Facility  
0
0
1
1
0
1
0
1
External Clocks  
Internal, 64kbps = f/16  
Internal, 32kbps = f/32  
Internal, 16kbps = f/64  
Table 3: Clock Mode  
1998 MX-COM, Inc.  
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054  
Doc. # 20480190.001  
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA  
All Trademarks and service marks are held by their respective companies.  
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