Delta Modulation CODEC
4
MX619
2 Signal List
J/P
1
LH
1
Name
Xtal/Clock
Signal
input
Description
Input to the clock oscillator inverter. A 1.024MHz Xtal input or
externally derived clock is injected here. See Clock Mode pins
and Figure 2.
No Connection
The 1.024 MHz output of the clock oscillator inverter.
No Connection
A logic I/O port. External encode clock input or internal data
clock output. Clock frequency is dependent upon Clock Mode 1,
2 inputs and Xtal frequency (see Clock Mode pins).
The encoder digital output. This is a three-state output whose
condition is set by the Data Enable and Powersave inputs. See
Table 2.
When this pin is at a logical “0” the encoder is forced to an idle
state and the encoder digital output is 0101, a perfect idle
pattern. When this pin is a logical “1” the encoder encodes as
normal. Internal 1MΩ pullup.
Data is made available at the encoder output pin by control of
this input. See Encoder Output pin. Internal 1 MΩ pullup.
No Connection
Normally at V
DD
/2 bias, this pin should be externally decoupled
by capacitor C4. Internally pulled to V
SS
when “ Powersave ” is
a logical “0”.
The analog signal input. Internally biased at V
DD
/2, this input
requires an external coupling capacitor. The source impedance
should be less than 100Ω. Output channel noise levels will
improve with an even lower source impedance. See Figure 2.
Negative Supply
No Connection
The recovered analog signal is output at this pin. It is the
buffered output of a lowpass filter and requires external
components. During “Powersave” this output is open circuit.
No Connection
A logic “0” at this pin puts most parts of the codec into a
quiescent non-operational state. When at a logical “1”, the
codec operates normally. Internal 1 MΩ pullup.
No Connection
A logic “0” at this pin gates a 0101... pattern internally to the
decoder so that the Decoder Output goes to V
DD
/2. When this
pin is a logical “1” the decoder operates as normal. Internal
1MΩ pullup.
The received digital signal input. Internal 1 MΩ pullup.
A logic I/O port. External decode clock input or internal data
clock output, dependent upon clock mode 1,2 inputs. See Clock
Mode pins.
A logic “1” at this pin sets this device for a 3-bit companding
algorithm. A logical “0” sets a 4-bit companding algorithm.
Internal 1 MΩ pullup.
2
3
4
2
3
4
5
N/C
Xtal
N/C
Encoder Data
Clock
Encoder Output
output
input/
output
output
5
6
6
7
Encoder Force Idle
7
8
9
8
9
10
Data Enable
N/C
V
BIAS
input
10
11
Encoder Input
input
11
12
13
12
13
14
V
SS
N/C
Decoder Output
power
output
14
15
15
16
N/C
Powersave
16
17
18
N/C
Decoder Force Idle
17
18
19
20
Decoder Input
Decoder Data
Clock
Algorithm
input/
output
19
21
2000
MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480189.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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CMLMICRO [ CML MICROCIRCUITS ]
