Low Voltage CTCSS Encoder/Decoder
4
MX465
2 Signal List
Pin No.
1
2
3
4
V
DD
XTAL/CLOCK
XTAL
Signal
Type
Description
power Positive supply. This pin should be bypassed to V
SS
by
a capacitor mounted close to the device pins.
input
Input to the on-chip inverter used with a 4 MHz Xtal or
external clock source.
Controls 8 on-chip latches. It is used to latch
RX / TX
,
PTL, and D0-D5. A logic 1 applied to this input places the
8 latches in the ‘transparent’ mode. A logic 0 applied to
this input places the 8 latches in the ‘latched’ mode. In
Parallel Mode, data is loaded and latched by a logic 1-0
transition (see Figure 4). In Serial Mode, data is loaded
and latched by a 0-1-0 strobe pulse on this pin (see
Figure 5). Internally pulled to V
DD
Data input D5 (Parallel Mode). A logic 1 applied to this
input together with a logic 0 applied to
D4/SERIAL ENABLE 2
will place the device in Serial
Mode (see Figure 5). Internally pulled to V
DD
.
Data input D4 (Parallel Mode). A logic 0 applied to this
input together with a logic 1 applied to D5 / SERIAL
ENABLE 1 will place the device in Serial Mode
(see Figure 5). Internally pulled to V
DD
.
Data input D3 (Parallel Mode). In Serial Mode this pin
becomes the serial data input for D5-D0,
RX/ TX
and PTL
(see Figure 5). D5 is clocked first and PTL last.
Internally pulled to V
DD
.
Data input D2 (Parallel Mode). In Serial Mode this pin
becomes the SERIAL CLOCK input. Data is clocked on
the positive going edge (see Figure 5). Internally pulled
to V
DD
.
Data input D1 (Parallel Mode). Internally pulled to V
DD
.
Data input D0 (Parallel Mode). Internally pulled to V
DD
.
Internally biased to V
DD
/3 or 2 V
DD
/3 via 1M resistors
depending on the logic state of the
RX TONE DECODE pin. RX TONE DECODE = 1 will
bias this input 2 V
DD
/3; a logic 0 will bias this input V
DD
/3.
This input provides the DECODE COMPARATOR
REFERENCE voltage, and the switching of bias voltages
provides hysteresis to reduce ‘chatter’ under marginal
conditions.
output Output of the on-chip inverter (clock output).
input
LOAD / LATCH
5
D5 / SERIAL ENABLE 1
input
6
D4 / SERIAL ENABLE 2
input
7
D3 / SERIAL DATA IN
input
8
D2 / SERIAL CLOCK
input
9
10
11
12
D1
D0
V
SS
DECODE COMPARATOR
REF.
input
input
input
power Negative supply.
13
RX TONE DECODE
output Gated output of the decode comparator. This output is
used to gate the RX Audio path. A logic 0 on this pin
indicates a successful decode and the DECODE
COMPARATOR IN pin is more positive than the
DECODE COMPARATOR REF. input (see Table 3).
input
Inverting input of the DECODE COMPARATOR. This pin
is normally connected to the integrated output of the RX
TONE DETECT line.
14
DECODE COMPARATOR IN
15
RX TONE DETECT
output In RX mode this output will go to logic 1 during a
successful decode. It must be externally integrated to
control response and deresponse times (see Table 3).
©1998 MX•COM, INC.
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Doc. #20480143.008
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