Variable Split Band Inverter
3
MX214/224
1.
Block Diagram
XTAL / CLOCK
INPUT LATCHES
EN / MUTE
CLEAR / SCRAMBLE
Rx / Tx
1MHz
1MHz
OSC
XTAL
POWERSAVE
LOAD / LATCH
SERIAL CLOCK
ENABLE / MUTE
CLEAR / SCRAMBLE
Rx / Tx (SER / PAR)
A0
A1
A2
A3
A4
(SERIAL DATA IN)
CK
B
EN
⋅
PS
⋅
Rx
Rx IN
PS
BIAS
Tx
⋅
PS
Tx
⋅
PS
Tx IN
FILTER 1
PS
BIAS
CK
A
C6
PS + EN
⋅
Rx
Tx
Tx
FILTER 2
CK
A
Rx
MUTE
BIAS
FILTER 3
CK
3
CTCSS
F
C2
C
5
FILTER 4
CK
4
Rx
F
C1
Rx
Tx
Rx
BIAS
Rx
PS + EN
⋅
Tx
Tx
SCRAMBLE
BIAS
CK
A
F
C1
F
C2
PS
CK
3
CK4
CK
B
CK
B
CLOCK
SWITCHING
Rx / Tx
ROM
CLOCK
DIVIDER
CLOCK
DIVIDER
V
DD
V
BIAS
V
SS
Rx
PS
⋅
EN
⋅
Tx
Tx OUT
Σ
CK
4
CLEAR
PS
⋅
MUTE
⋅
Rx
Rx OUT
BIAS
BIAS
Figure 1: Block Diagram
1998
MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480112.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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