Variable Split Band Inverter
4
MX214/224
2.
Signal List
MX224
Pin No.
J/P
LH
1
1
Signal Name
Description
MX214
Pin No.
J/P
LH
7
1
Xtal/Clock
8
9
2
3
2
2
Xtal
Serial Data Input
Input to the clock oscillator inverter. A 1MHz crystal
input or externally derived 1MHz clock is injected
here.
Output of the clock oscillator inverter.
This pin is used to input an 8-bit word representing
the digital control functions. This word is loaded
using the serial data clock and in input in the
following sequence: MUTE, CLEAR, Rx / Tx , A0,
A1, A2, A3, A4. The Load / Latch is operated on the
completion. Reference the timing diagram in Figure
8.
In parallel mode, these five digital inputs define the
split point frequency. Each of the 5 input pins has a
1M internal pull-up resistor. See Table 4 for
programming information.
This digital input selects the Receive and Transmit
paths and configures upperband and lowerband
filter bandwidths while setting the CTCSS highpass
filter position on the signal path. See Table 2,
Figure 6, and Figure 7. 1M internal pull-up resistor
(Rx).
This pin must be connected to V
SS
for serial loading.
Internal 1M pull-up resistor.
This digital input puts the device into ‘Clear’ or
‘Scramble’ mode by controlling the application of
carrier frequency to the Upper and Lower band
balanced modulators. In ‘Scramble’ mode, the
balanced modulator carrier frequency values are
selected by the split point address A0-A4. See
Table 4. In ‘Clear’ mode, the carriers are disabled
and the balanced modulators are bypassed
internally, i.e. the lower band signal is not added to
the output signal. 1MHz internal pull-up resistor
(Clear).
This digital function is used to disable the Receive or
the Transmit signal paths for rolling code
synchronization while maintaining bias conditions.
Synchronization data can be transmitted during the
Mute periods, as is done in the MX1204 VSB
Scrambler Module. 1M Internal pull-up resistor
(Enable)
This is the externally applied data clock frequency
used to shift input data along in devices wired in the
Serial-loading mode. One full data clock cycle is
required to shift one data bit completely into the
register. See Timing Diagram Figure 8. 1M
Internal pull-up resistor.
3 – A4
4 – A3
5 – A2
6 – A1
7 – A0
8
3 – A4
4 – A3
5 – A2
6 – A1
7 – A0
8
Programming
Inputs
Rx / Tx
13
8
9
9
Parallel / Serial
Clear/Scramble
10
10
Enable/Mute
14
10
Serial Clock
Input
1998
MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480112.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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