Audio Band Scrambler
FX/MX128
1.3
Pin No.
1
2
3
4
5
Signal List
Signal
Name
XTALN
XTAL/CLOCK
-
TXOUT
TX GAIN AMP
OUT
TXIN
-
V
SS
V
BIAS
-
RXIN
RX GAIN AMP
OUT
RXOUT
CLR
CLOCK
SELECT
V
DD
I/P
O/P
N/C
=
=
=
Type
O/P
I/P
N/C
O/P
O/P
Description
All
Packages
6
7
8
9
10
11
12
13
14
15
16
Notes:
I/P
N/C
Power
O/P
N/C
I/P
O/P
O/P
I/P
I/P
Power
Input
Output
This is the output of the clock oscillator inverter.
10.24 MHz, 3.58/3.6864 MHz, or an externally derived clock is
injected at this pin. See Figure 1.
No connection should be made to this pin.
This is the analogue output of the transmit channel. It is internally
biased at V
DD
/2.
This is the output pin of the transmit channel gain adjusting op-
amp.
See Figure 3 for gain setting components.
This is the analogue signal input to the transmit channel. This
input goes to a gain adjusting op-amp whose gain is set by
external components. See Figure 3.
No connection should be made to this pin.
Negative supply (GND)
This is an internally generated bias voltage output (V
DD
/2).
It should NOT be decoupled with a capacitor.
No connection should be made to this pin.
This is the analogue signal input to the receive channel. This
input goes to a gain adjusting op-amp whose gain is set by
external components. See Figure 3.
This is the output pin of the receive channel gain adjusting op-
amp. See Figure 3 for gain setting components.
This is the analogue output of the receive channel. It is internally
biased at V
DD
/2.
A logic 1 on this input selects the invert mode. A logic 0 selects
the clear (not inverted) mode.
Selects either 10.24 or 3.58/3.6864 MHz clock frequency. A logic
“1” selects 10.24 MHz, and a logic “0” selects 3.58/3.6864 MHz.
This input is internally pulled high.
Positive supply of 3.0V to 5.5 V
No Connection
©
2003 CML Microsystems Plc
4
D/128/2
CMLMICRO [ CML MICROCIRCUITS ]
