Autocorrelating Signal Processor
4
MX102
2. Signal List
Packages
DW/J
1
Signal
Name
Signal In
Type
input
The inverting input to the analog amplifier/comparator. Used with the
Signal Bias pin; external coupling components are required.
See Figure 2
The output of the analogue amplifier/comparator. Do not load this pin with
peripheral circuitry; there is no drive capacity for off-chip signaling. The
feedback resistor should be not less than 200kΩ. See Figure 2.
Positive supply rail. A single, stable power supply is required. Note that
this device has two V
DD
pins; this input is positioned to prevent cross-talk,
either or both may be connected to the host circuit's supply line. Do not
attempt to draw current from either V
DD
pin.
Buffered inverter oscillator digital output. May be used as test point to
align clock frequency or to drive other circuitry.
The output of the on-chip clock oscillator inverter.
The input to the on-chip clock oscillator inverter; this may be a Xtal,
resonator or clock pulse input. The selection of this frequency will affect
the operational input signal bandwidth (and output frequency) of this
device; refer to Table 4. Note that the choice of V
DD
will determine the
maximum Xtal/clock frequency and hence the maximum useable signal
input frequency. Operation of this microcircuit without an active Xtal or
clock input may cause device damage. A clock pulse input is fed directly
into this pin; Xtal/clock components are not required.
See Table 2.
Negative Supply
A squarewave output clock signal at the rate of Clock/6; provided for
peripheral and test purposes.
(fOUT = 4 x fSIGNAL IN). The auto-correlated output signal at four times
(x 4) the input signal (see Figure 3).
There is a time delay between input and output signals (see
Specifications).
Positive supply rail. A single, stable power supply is required.
Note that this device has two V
DD
pins; either or both may be connected
to the host circuit's supply line. Do not attempt to draw current from either
V
DD
pin.
The choice of V
DD
will determine the maximum Xtal/clock frequency and
hence the maximum useable signal input frequency (see Figure 4).
2, 7, 10, 12, 14, 15
N/C
No internal connection. Leave open circuit
Table 1: Signal List
Description
3
Signal
Bias
V
DD
output
4
power
5
6
8
BUFCLK
output
output
input
XTAL
Xtal/Clock
9
11
13
V
SS
CLK ÷ 6
OUTPUT
power
output
output
16
V
DD
power
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