FRS Signalling Processor
CMX882
C-BUS Timing
Figure 14 C-BUS Timing
Notes
C-BUS Timing
Min.
100
100
0.0
Typ.
Max.
Unit
tCSE
tCSH
tLOZ
CSN Enable to SClk high time
ns
ns
ns
Last SClk high to CSN high time
SClk low to ReplyData Output Enable
Time
tHIZ
CSN high to ReplyData high impedance
CSN high time between transactions
Inter-byte time
1.0
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
tCSOFF
tNXT
tCK
1.0
200
200
100
100
75
SClk cycle time
tCH
SClk high time
tCL
SClk low time
tCDS
tCDH
tRDS
tRDH
Command Data setup time
Command Data hold time
Reply Data setup time
Reply Data hold time
25
50
0
Notes: 1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the
peripheral MSB (Bit 7) first, LSB (Bit 0) last. REPLY DATA is read from the peripheral
MSB (Bit 7) first, LSB (Bit 0) last.
2. Data is clocked into the peripheral on the rising SERIAL_CLOCK edge.
3. Commands are acted upon at the end of each command (rising edge of CSN).
4. To allow for differing µC serial interface formats C-BUS compatible ICs are able to work
with SERIAL_CLOCK pulses starting and ending at either polarity.
5. Maximum 30pF load on IRQN pin and each C-BUS interface line.
These timings are for the latest version of C-BUS and allow faster transfers than the original C-BUS
timing specification. The CMX882 can be used in conjunction with devices that comply with the slower
timings, subject to system throughput constraints.
2004 CML Microsystems Plc
67
D/882/7
CMLMICRO [ CML MICROCIRCUITS ]
