FRS Signalling Processor
CMX882
Block 1 – XTCSS and In-band tone Setup:
Bit:
15
1
14
1
13
0
12
1
11
10
9
8
7
6
5
4
3
2
1
0
P1.0
Audio band Tx level
Emph
XTCSS
In-band tone detect
bandwidth
P1.1
0
1
0
1
Audio band detect threshold
tone length
P1.2
P1.3
P1.4
P1.5
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
Programmable In-band Tone 0
Programmable In-band Tone 1
Programmable In-band Tone 2
Programmable In-band Tone 3
Block 2 – CTCSS and DCS Setup:
Bit:
15
1
14
1
13
1
12
0
11
10
0
9
8
7
6
5
4
3
2
1
0
P2.0
CTCSS and DCS Tx level
CTCSS detect
bandwidth
DCS
24
P2.1
0
1
1
0
CTCSS and DCS detect threshold
P2.2
P2.3
P2.4
0
0
0
1
1
1
1
1
1
0
0
0
DCS Code bits 11 – 0
DCS Code bits 23/22 – 12
Sub-audio drop out
time
0
Block 3 – Reserved. Do not use.
Block 4 – Gain and Offset Setup:
Bit:
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P4.8
15
1
0
0
0
0
0
0
0
0
14
0
0
0
0
0
0
0
0
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Fine Input Gain
Reserved - set to '0'
Fine Output Gain 1
Fine Output Gain 2
Output 1 Offset Control
Output 2 Offset Control
Ramp Rate Control
Limiter Setting (all 1's = Vbias +/- 0.5 Vdd)
Special Programming Register (Production Test Only)
2004 CML Microsystems Plc
51
D/882/7
CMLMICRO [ CML MICROCIRCUITS ]
