FRS Signalling Processor
CMX882
0
1.6.10
$C3 Tx In-Band Tones: 16-bit write-only
15
14
13
12
11
10
9
8
0
7
6
0
5
4
0
3
0
2
0
1
0
Bit:
Bits 15 to 11 defTinxeIn-tbhaendtotonnee transmitted0when0Tx In-band 0tone is enab0led. The frequency is as defin0ed in
Table 6 In-band Tones.
Bits 10 to 1 are reserved, set to '0'.
1.6.11
$C7 Modem Control: 16-bit write-only
Bit:
15
0
14
0
13
0
12
0
11
0
10
9
8
0
7
6
5
4
0
3
0
2
1
0
Type 0
format
Last Tx
data
MSK message
format
User
bit
Scramble
seed
This register configures the way the CMX882 handles MSK data in both transmit and receive.
Bits 15 to 11, 8, 4 and 3 are reserved, set to '0'.
Bit 10 sets the raw data mode when set to '1'. When set to '0' the built in data packeting is enabled. The
way this bit is set determines how the CMX882 handles new data when transmit and receive modes:
Bit 10, Receive mode:
•
If Bit 10 is ‘1’ the device will look for the programmed Frame Sync. pattern, raise an interrupt (if
enabled) and decode the following data 16 bits at a time, making them available in register $C5.
•
If Bit 10 is ‘0’ the device will look for a complete Frame Head before raising an interrupt (if
enabled) and then decode the following data in accordance with the received message format.
The Frame Head Control Field bytes, User Data and any CRC will be presented in registers $C5
and $C9.
Bit 10, Transmit mode:
•
If Bit 10 is ‘1’ the device will transmit data 16 bits at a time from register $CA. Bit and frame sync
pattern generation and all formatting of the data have to be performed by the host in this case.
•
If Bit 10 is ‘0’ the device will transmit the programmed bit and frame sync patterns followed by a
Frame Head containing the information supplied in bits 7–0 of this register and the 2 bytes in
register $CA. Subsequently the host must supply data when requested to complete the
transmission of the data packet as defined in the Frame Head bytes.
Bit 9 is only valid when transmitting data with type 0, 2 or 3 formatting and indicates to the CMX882 that it
can cease modulation. The host must set this bit to '1' immediately after the interrupt for ‘load more data’
occurs. In receive, or when transmitting other message formats, this bit must be set to '0'.
When bit 10 = ‘0’ bits 7-0 control the format and coding used for MSK messages: (See also section
1.5.5.)
Bits 7 to 5 control the data formatting used by the CMX882 in transmit and receive:
Bit 7
Bit 6
Bit 5
Type
Message format:
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
1
2
3
4
5
-
Frame Head only, no payload
Frame Head + Unsized payload of raw 16 bit words
Frame Head + Unsized payload with FEC
Frame Head + Sized payload with FEC + CRC
Frame Head + Sized payload with FEC + CRC + interleaving
Reserved
All other patterns
2004 CML Microsystems Plc
43
D/882/7
CMLMICRO [ CML MICROCIRCUITS ]
