FRS Signalling Processor
CMX882
1.6.4
$B1 SIGNAL ROUTING: 16-bit write-only
Bit:
15
14
13
12
11
10
9
8
7
0
6
0
5
4
3
2
1
0
Tx MOD_1 and
MOD_2 Routing
Analogue
i/p select
AUDIO
Ramp Ramp
Up Down
0
0
0
0
0
0
o/p select
Bits 15 and 14 reserved - set to 0.
Bits 13 and 12 select the routing of the transmit signals allowing 1 or 2 point modulation and interfaces.
Bit 13 Bit 12
Tx MOD_1 and MOD_2 routing
0
0
1
1
0
1
0
1
Tx, MOD_1 and MOD_2 outputs set to bias.
Tx, In band signals to MOD_1, Subaudio signals to MOD_2
Tx, In band and Subaudio to MOD_1, MOD_2 set to bias
Tx, In band and Subaudio to both MOD_1 and MOD_2
‘In-band’ in this context refers to any of the signals; Voice, In-band tone etc.
Bits 11 to 6 are reserved - set to 0.
Bit 5
Bit 4
Analogue Input select
0
0
1
1
0
1
0
1
No input selected (Input = VBIAS
Input amplifier 2 (Input_2 i/p)
Microphone (MIC i/p)
)
Discriminator (DISC i/p)
Bit 3
Bit 2
AUDIO Output select
0
0
1
1
0
1
0
1
No output selected (Output = VBIAS
)
Received Voice signal
MOD_1 signal (for Tx monitoring)
Reserved, do not use
When bits 1 or 0 are set to '1' output signals are ramped up (bit 1) or ramped down (bit 0) to reduce
transients in the transmitted signal. Time to ramp up / down is set in the 'Ramp Rate Control' section of
the Programming register (P4.6).
1.6.5
$B2 AUXILIARY ADC THRESHOLDS: 16-bit write-only
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
High Threshold [Range: 0 to 255]
Low Threshold [Range: 0 to 255]
If the selected signal level exceeds the High Threshold, the ‘Signal High’ bit of the Status register will be
set to 1. If the Signal level falls below the Low Threshold, the ‘Signal Low’ bit of the Status register will
be set to 1. If the corresponding interrupt bit is enabled, a C-BUS interrupt will be generated. These
status bits are cleared when the Status register is read. The behaviour of the CMX882 is not defined if
the high threshold is less than the low threshold.
Threshold resolution:
Threshold accuracy:
Differential linearity:
VDD(A)/256 per LSB
±2 LSB
±1 LSB [monotonic]
The ‘Auxiliary ADC Thresholds’ register must not be updated whilst the Auxiliary ADC is enabled.
2004 CML Microsystems Plc
38
D/882/7
CMLMICRO [ CML MICROCIRCUITS ]
