FRS Signalling Processor
CMX882
1.3
Signal List (continued)
Package
D6, E1
Signal
Name
Description
Pin No.
Type
10
VBIAS
O/P
Internally generated bias voltage of approximately VDD(A)/2,
except when bias is power-saved when VBIAS will discharge
to VSS(A)
.
This pin should be decoupled to VSS(A) by a
capacitor mounted close to the device pins.
11
12
13
DISC
I/P
O/P
I/P
Input terminal of discriminator input amplifier.
Output / feedback terminal of discriminator input amplifier.
DISC_FB
INPUT_2
Input terminal of amplifier 2, for either a second microphone
or discriminator input.
14
15
16
17
19
20
22
24
INPUT_2_FB
MIC
O/P
I/P
Output / feedback terminal of input amplifier 2.
Input terminal of microphone input amplifier.
Output / feedback terminal of microphone input amplifier.
Signal Monitor input to the internal level detecting circuit.
Modulator 1 output.
MIC_FB
O/P
I/P
SIG_MONITOR
MOD_1
O/P
O/P
O/P
I/P
MOD_2
Modulator 2 output.
AUDIO
Output of the audio section.
CLOCK/XTAL
The input to the on-chip oscillator for an external crystal or a
clock circuit.
25
CLOCK_OUT
O/P
Buffered (un-inverted) clock output available for use by
other devices in the system.
26
I/P
Test input, connect to VSS(D).
27, 28
NC
No connection should be made to these pins.
Notes: I/P
=
Input
O/P = Output
T/S
NC
=
=
3-state Output
No Connection
2004 CML Microsystems Plc
10
D/882/7
CMLMICRO [ CML MICROCIRCUITS ]
