TETRA Baseband Processor
FX980
1.3
Signal List
Package
#
Pin No.
L6 Package
44 PLCC
Pin No.
15
16
17
18
19
20
11
12
23
14
24
25
26
30
29
42
41
38
37
43
44
1
2
Signal
Name
MCLK
SClk
CmdDat
CmdFS
CmdRdDat
CmdRdFS
RxDat
RxFS
N_IRQ
N_RESET
SCANSEL
ITXP
ITXN
QTXP
QTXN
IRXP
IRXN
QRXP
QRXN
AUXADC1
AUXADC2
AUXADC3
AUXADC4
Type
I/P
O/P
BI
I/P
O/P
O/P
O/P
O/P
O/P
I/P
I/P
O/P
O/P
O/P
O/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
I/P
Description
Master clock input (typically 9.216MHz)
Serial interface clock
Command serial interface Data
Command serial interface Frame
Command serial interface Read Data
Command serial interface Read Frame
Receive serial interface Data
Receive serial interface Strobe
Interrupt request
Chip Reset
Scan Select (normally tied low)
Transmit "I" channel, positive output
Transmit "I" channel, negative output
Transmit "Q" channel, positive output
Transmit "Q" channel, negative output
Receive "I" channel, positive input
Receive "I" channel, negative input
Receive "Q" channel, positive input
Receive "Q" channel, negative input
Auxiliary ADC channel 1
Auxiliary ADC channel 2
Auxiliary ADC channel 3
Auxiliary ADC channel 4
©
1997
Consumer Microcircuits Limited
4
D/980/3
CMLMICRO [ CML MICROCIRCUITS ]
