4-Level FSK Modem Data Pump
FX919A
1.5
1.5.1
General Description
Description of Blocks
Data Bus Buffers
Eight bidirectional 3-state logic level buffers between the modem's internal registers and the host µC's data bus
lines.
Address and R/W Decode
This block controls the transfer of data bytes between the µC and the modem's internal registers, according to
the state of the Write and Read Enable inputs (WRN and RDN), the Chip Select input (CSN) and the Register
Address inputs A0 and A1.
The Data Bus Buffers, Address and R/W Decode blocks provide a byte-wide parallel µC interface, which can
be memory-mapped, as shown in Figure 3.
Figure 3 Typical Modem µC Connections
Status and Data Quality Registers
Eight-bit registers which the µC can read to determine the status of the modem and the received data quality.
Command, Mode and Control Registers
The values written by the µC to these 8-bit registers control the operation of the modem.
Data Buffer
A 12-byte buffer used to hold receive or transmit data to or from the µC.
CRC Generator/Checker
A circuit which generates (in transmit mode) or checks (in receive mode) the Cyclic Redundancy Checksum
bits, which may be included in transmitted data blocks so that the receive modem can detect transmission
errors.
©
1996 Consumer Microcircuits Limited
7
D/919A/4
CMLMICRO [ CML MICROCIRCUITS ]
