Wireless Modem Data Pump
FX909A
1.6.2
Receive Frame Example
If the device is required to decode a Mobitex Frame the following control signals should be issued to
the modem, assuming the device is initially not in powersave, PLLBW, LEVRES, SCREN are set as
required, TXRXN bit is set to '0', the Frame Sync bytes have not been set and the carrier has been
detected, or a Frame Head is imminently expected:
1. 2 Frame Sync bytes are loaded.
2. 2 bits after the carrier has been detected, a LFSB task is loaded, along with setting the AQLEV
and AQBC bits, to initiate the level acquisition and bit clock extraction sequences.
3. Device interrupts host µC with IRQN when 2nd byte is read from Data Buffer.
4. Status Register is read, 12 bits later task is set to SFH to search for a Mobitex Frame Head.
5. Device will interrupt host µC with IRQN when valid Frame Sync is detected and header bytes
decoded.
6. Host µC reads Status Register, checks MOBAN and CRCFEC bit and reads out 2 Frame Head
control bytes.
7. Host µC sets the task to RDB to receive a Mobitex Data Block.
8. Device will interrupt host µC with IRQN when the Data Block has been received and the CRC
has been calculated.
9. Host µC reads Status Register, checks CRC validity and reads 18 Data Block bytes. The Data
Quality Register can also be read to obtain the received S/N level.
10. Host µC sets task if more information is expected:
GOTO '4' if last Data Block and another Frame Head imminently expected.
GOTO '7' if another Mobitex Data Block expected.
If the last Data Block has been decoded and no more information is expected then the task bits need
not be set as the device will automatically select the idle state.
A top level flowchart of the receive process is shown in Figure 15.
ã 1996 Consumer Microcircuits Limited
34
D/909A/4
CMLMICRO [ CML MICROCIRCUITS ]
