Wireless Modem Data Pump
FX909A
The µC should not write a task (other than NULL or RESET) to the Command Register or write to or
read from the Data Buffer when the BFREE (Buffer Free) bit of the Status Register is '0'.
Different tasks apply in receive and transmit modes.
When the modem is in transmit mode, all tasks other than NULL, RESET and TSO instruct the
modem to transmit data from the Data Buffer, formatting it as required. For these tasks the µC should
wait until the BFREE (Buffer Free) bit of the Status Register is '1', before writing the data to the Data
Buffer, then it should write the desired task to the Command Register. If more than 1 byte needs to
be written to the Data Buffer, byte number 0 of the block should be written first.
Once the byte containing the desired task has been written to the Command Register, the modem
will:
Set the BFREE (Buffer Free) bit of the Status Register to '0'.
Take the data from the Data Buffer as quickly as it can - transferring it to the Interleave Buffer
for eventual transmission. This operation will start immediately if the modem is 'idle' (i.e. not
transmitting data from a previous task), otherwise it will be delayed until there is sufficient room
in the Interleave Buffer.
Once all of the data has been transferred from the Data Buffer the modem will set the BFREE
and IRQ bits of the Status Register to '1', (causing the chip IRQN output to go low if the
IRQNEN bit of the Mode Register has been set to '1') to tell the µC that it may write new data
and the next task to the modem.
In this way the µC can write a task and the associated data to the modem while the modem is still
transmitting the data from the previous task. See Figure 7.
When the modem is in receive mode, the µC should wait until the BFREE bit of the Status Register is
'1', then write the desired task to the Command Register.
Once the byte containing the desired task has been written to the Command Register, the modem
will:
Set the BFREE bit of the Status Register to '0'.
Wait until enough received bits are in the De-interleave Buffer.
Decode them as needed, and transfer any resulting data to the Data Buffer
Then the modem will set the BFREE and IRQ bits of the Status Register to '1', (causing the
IRQN output to go low if the IRQNEN bit of the Mode Register has been set to '1') to tell the µC
that it may read from the Data Buffer and write the next task to the modem. If more than 1 byte
is contained in the Data Buffer, byte number '0' of the data will be read first.
In this way the µC can read data and write a new task to the modem while the received bits needed
for this new task are being stored in the De-interleave Buffer. See Figure 8.
The above is not true for loading the Frame Sync detection bytes (LFSB): the bytes to be compared
with the incoming data must be loaded prior to the task bits being written.
Detailed timings for the various tasks are given in Figures 9 and 10.
ã 1996 Consumer Microcircuits Limited
15
D/909A/4
CMLMICRO [ CML MICROCIRCUITS ]
