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FX805LS 参数 Datasheet PDF下载

FX805LS图片预览
型号: FX805LS
PDF下载: 下载PDF文件 查看货源
内容描述: 亚音频信令处理器 [Sub-Audio Signalling Processor]
分类和应用: 电信集成电路电信电路
文件页数/大小: 17 页 / 166 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
 浏览型号FX805LS的Datasheet PDF文件第9页浏览型号FX805LS的Datasheet PDF文件第10页浏览型号FX805LS的Datasheet PDF文件第11页浏览型号FX805LS的Datasheet PDF文件第12页浏览型号FX805LS的Datasheet PDF文件第14页浏览型号FX805LS的Datasheet PDF文件第15页浏览型号FX805LS的Datasheet PDF文件第16页浏览型号FX805LS的Datasheet PDF文件第17页  
Timing Information  
Timing Diagrams  
Figure 9 shows the timing parameters for two-way communication between the µController and the FX805 on the “C-BUS.”  
Figure 10 shows, in detail, the timing relationships for “C-BUS” information transfer.  
t CSOFF  
CHIP SELECT  
t CSE  
t NXT  
t NXT  
t CK  
t CSH  
SERIAL CLOCK  
COMMAND DATA  
7
6
5
4
3
2
1
0
7
6
6
5
4
3
2
1
1
0
7
7
6
6
5
4
3
2
1
1
0
0
MSB  
LSB  
ADDRESS/COMMAND  
BYTE  
FIRST DATA BYTE  
LAST DATA BYTE  
REPLY DATA  
t HIZ  
7
5
4
3
2
0
5
4
3
2
MSB  
LSB  
FIRST REPLY DATA BYTE  
LAST REPLY DATA BYTE  
Logic level is not important  
Fig.9 “C-BUS” Timing Information  
NOT TO SCALE  
Parameter  
Min.  
Typ.  
Max.  
Unit  
tCSE  
tCSH  
tCSOFF  
tNXT  
tCK  
2.0  
4.0  
2.0  
4.0  
2.0  
500  
500  
250  
0
µs  
µs  
µs  
µs  
µs  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
tCH  
tCL  
tCDS  
tCDH  
tRDS  
tRDH  
tHIZ  
250  
50.0  
2.0  
Notes  
(1) Command Data is transmitted to the peripheral MSB (bit 7) first, LSB (bit 0) last.  
Reply Data is read from the FX805 MSB (bit 7) first, LSB (bit 0) last.  
(2) Data is clocked into the FX805 and into the µController on the rising Serial Clock edge.  
(3) Loaded data instructions are acted upon at the end of each individual, loaded byte.  
(4) To allow for differing µController serial interface formats, the FX805 will work with either polarity Serial  
Clock pulses.  
tCK  
tCL  
70% V  
DD  
SERIAL CLOCK  
(from µC)  
30% V  
DD  
tCH  
tCDH  
tCDS  
COMMAND DATA  
(from C)  
µ
tRDH  
tRDS  
REPLY DATA  
(to C)  
µ
Fig.10 “C-BUS” Timing Relationships  
NOT TO SCALE  
13