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FX805LG 参数 Datasheet PDF下载

FX805LG图片预览
型号: FX805LG
PDF下载: 下载PDF文件 查看货源
内容描述: 亚音频信令处理器 [Sub-Audio Signalling Processor]
分类和应用: 电信集成电路电信电路
文件页数/大小: 17 页 / 166 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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Controlling Protocol ......  
“Read NRZ Rx Data Register” – A/C 74H (7CH), followed by 1 byte of Reply Data.  
Received NRZ data bits are organized into bytes and  
made available to the µController via the Reply Data line. As  
8 bits are received into this register an interrupt is generated  
to indicate that a complete byte has been received, this byte  
must be read before the arrival of the last (8th) bit of the next  
incoming byte, if this is not done, an interrupt to indicate this  
condition will be generated and the previous Rx data is  
discarded (See Table 4, Status Register, Bits 2 and 3).  
Word synchronization is not provided. Byte  
synchronization and any codeword recognition will be  
performed by the host µController. The Rx baud rate is set  
by writing to the CTCSS Tx Frequency/NRZ Baud Rate  
Register (73H/7BH). The first bit received is the first bit sent to  
the µController.  
This register is not affected by the General Reset  
command (01H) and may adopt any random configuration at  
Power-Up.  
“Write to NRZ Tx Data Register” – A/C 75H (7DH), followed by 1 byte of Command Data.  
A byte for transmission is loaded from the “C-BUS”  
Command Data line with this A/C. The first data-bit received  
via the “C-BUS” is transmitted first. This transmitter  
operation is non-inverting.  
Transmission is terminated, the Tx Sub-Audio Output placed  
at VBIAS, and an interrupt generated if the next byte is not  
loaded within 7 bit periods. (See Table 4, Status Register,  
Bits 4 and 5).  
The first data-byte loaded after the NRZ Encoder is  
enabled (Control Register) initiates the transmission  
sequence and an interrupt will be generated when the NRZ  
Tx Data Buffer is ready for the next data-byte.  
This register is not affected by the General Reset  
command (01H) and may adopt any random configuration at  
Power-Up.  
Subsequently, interrupts occur for every 8 bits transmitted.  
“Write to Gain-Set Register” – A/C 76H (7EH), followed by 1 byte of Command Data.  
Setting  
Gain Setting  
The Gain-Set Register Settings  
The settings of this register control the CTCSS and NRZ  
signal level that is presented at the Tx Sub-Audio Output.  
MSB  
7
6
5
4
Transmitted Bit 7 First  
0
0
0
0
These 4 Bits Must be “0”  
Bit 3, when enabled, is used to produce a pre-emphasis  
effect on the NRZ Tx Data by increasing the gain of the data  
bit before a level change (Figure 8 below), by 1.72dB to  
make that data pulse level slightly more positive (or  
negative). The signal level will be 1.72dB greater than that  
set by Bits 0 to 2. If the Tx Sub-Audio Output level is set to  
+2.58dB, the pre-emphasized level will be +4.3dB.  
3
1
0
Pre-Emphasis Setting  
1.72dB Gain Enabled  
1.72dB Gain Disabled  
2
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
1
Tx Level Adjust Gain Setting  
The pre-emphasis function, will remain enabled until  
disabled by setting Bit 3 to a logic “0.” If this function remains  
enabled when using the CTCSS Encoder the output signal  
level may be adversely affected, therefore this function  
should only be enabled when in the NRZ Encode mode.  
0
0
1
1
0
0
1
1
-2.58  
-1.72  
-0.86  
0
dB  
dB  
dB  
dB  
dB  
dB  
dB  
This register is not affected by the General Reset  
command (01H) and may adopt any random configuration at  
Power-Up.  
+0.86  
+1.72  
+2.58  
Not Used  
Table 7 Gain-Set Register Settings  
NRZ Tx DATA  
BIT PERIODS  
GAIN-SET NRZ Tx DATA with PRE-EMPHASIS ENABLED  
Gain-Set  
+1.72dB  
Gain-Set  
Gain-Set  
+1.72dB  
Gain-Set  
+1.72dB  
+1.72dB  
Fig.8 Gain-Set with Pre-Emphasis  
12