SPM and Security Subsystem
FX651
1.5
1.5.1
General Description
Overall Function
The FX651 is a dual channel tone detector for use in the French Payphone system where 12kHz SPM
and 18kHz security tones are used.
SPM (12kHz) Detector
The SPM detector channel responds to a low level (50mV) 12kHz tone in the presence of a large
security tone (16kHz - 20kHz) and speech.
The device responds after a period of continuous valid tone and so recognises a valid SPM toneburst
(minimum transmission duration, 75ms).
This function is permanently enabled.
Security Tone (18kHz) Detector (Rx Mode Only)
This demodulates the 18kHz ASK signal in the presence of the SPM signalling.
Security Tone Transmission (Tx Mode Only)
An 18kHz tone modulated ON - OFF by the NRZ data pin. A logic low gates the signal ON so that
18kHz is transmitted. A logic high gates the signal OFF so that no tone appears at the TXOP pin.
1.5.2
Description of Blocks
(
See Figure 1)
Input Amplifier
This amplifier is connected as a differential amplifier and is used to couple the signal into the device. It
also attenuates the combined speech, SPM tone and security tone to prevent its output saturating. Its
signal gain should be -10dB at 5.0V supply and -13dB at 3.3V.
(See Figure 2 for recommended component values)
Sample and Hold (12kHz Channel)
This samples the input signal at 17.898kHz and creates images of the incoming frequencies. The
12kHz SPM is translated to 5.898kHz and the security tone is translated to between 978Hz and
1182Hz. This simplifies the subsequent signal processing.
Filtering and Frequency Detection (12kHz Channel)
The output of the sample and hold circuit is passed to filter HPF1. This is a switched capacitor high
pass filter which amplifies the frequency shifted SPM tone (about 5.9kHz) but rejects the frequency
shifted security tone (about 1kHz). The filter also rejects any speech signals present. The filter output
is passed to the level detect and frequency measurement circuitry which determines the presence or
absence of a valid SPM signal on the line. A valid signal sends the "DETECT 12kHz" pin to logic low.
Sample and Hold (18kHz Channel)
This samples the input signal at 71.592kHz. It is synchronised with the following high pass filter, which
is a switched capacitor circuit with the same sampling rate. The sample and hold circuit stores the
value of the input waveform value between sampling instants so that it is a suitable input for the filter.
Without the sample and hold circuit, speech or SPM tone components which are large compared with
the security tone would interfere with the level discrimination at the filter output.
©
1997 Consumer Microcircuits Limited
7
D/651/4
CMLMICRO [ CML MICROCIRCUITS ]
