Pin Number
FX631 FX631
D5 DW/P
1
1
Function
Xtal/Clock:
The input to the on-chip clock oscillator; for use with a 3.579545MHz Xtal in
conjunction with the Xtal output (see Figure 2); circuit components are on chip. Using this mode
of clock operation, the
Description
pin should be connected directly to the Clock In pin. If a clock
2.3 Pin Function
Clock Out
pulse input is employed to the Clock In pin, this pin must be connected directly to V
DD
(see
Figure
XTAL The input of the oscillator inverter.
2).
Xtal:
The output of the on-chip clock oscillator inverter.
CLKIN The input to the internal clock divider circuitry.
When a 3.579545MHz crystal is used, it should be connected across XTAL & XTAL and XTAL
Clock Out:
A clock signal derived from the on-chip Xtal oscillator. If the on-chip oscillator is
should be directly connected to CLKIN. No other external components are necessary because
used, this pin should be connnected directly to the Clock In pin. This output should not be used
the other oscillator components (capacitor, resistor) are on chip.
to clock other devices.
When an externally available clock signal is used, it should be inserted at CLKIN. XTAL should
be tied to VDD or Vss and XTAL should be left open circuit.
XTALN The output of the oscillator inverter
4
5
2
3
6
4
Clock In:
The 3.579545MHz clock pulse input to the internal clock-dividers. If a clock pulse
SYSTEM A logic
Xtal/Clock input (Pin
whether the device detects 12Khz SPM tones
2.
input is employed, the
input pin which controls
1) should be connected to V
DD
. See Figure
(logic 1)
or 16Khz SPM tones (logic 0). It has an internal 1 Mohm pull- up resistor (l 2Khz).
NEGIP The negative input,
analogue bias circuitry. Held internally
gain adjusting POSIP
V
BIAS
:
The output of the on-chip
positive input and output respectively of the
at V
DD
/2, this pin should
amplifier.
be decoupled to V
SS
(see Figure 2).
AMPOP
External components are used in conjunction with the op -amp according to the required level
V
SS
:
Negative supply rail (GND).
whether the incoming signal is differential or common mode.
sensitivity and depending on
8
7
12
13
17
18
19
8
9
10
11
13
VDD
The
power supply,
negative signal inputs to, and the output from, the input gain
The
positive and
ground and filter bias pins respectively.
Signal In (+):
VSS
adjusting signal amplifier. Refer to the graph in Figure 4 for guidance on
BIAS
setting level sensitivities
be
national specifications, and the selection of gain
Voo and bias should each
to
de- coupled, via a 1 .0@F capacitor, to VSS.
Signal In (-):
Amp Out:
adjusting components.
TTFOP TRUE TONE FOLLOWER OUTPUT. This is the pin that responds and de-
responds within 4ms of a good tone appearing or disappearing.
It is thus
Output:
This
of the
provides
Tone Follower
like an envelope
output
SPM tone.
a logic “0” (Low) for the period of a detected tone,
and a logic “1” (High) for N
OTONE
detection. See Figure 7.
· logic 0 represents ‘detect’ and logic 1 represents ‘not detect’.
20
14
DTFOP This
logic output that
‘delayed tone follower’
a cumulation of 40ms of 'good'
Packet Mode Output:
A
is the output of the
will be available after
block.
tone has been received. This packet mode tone follower will only respond when a tone
It will respond when 40ms of good tone has been
sufficient time, i.e. a cumulation of
48ms
in
frequency of sufficient quality has been received for
received within any 48ms window. The
40ms
is
divided into 24 ‘packets’ of
breaks will be ignored. This output
of 2.667ms each (12Khz
any 48ms, short tone bursts or
2ms each (16Khz mode) or 15 ‘packets’
provides a logic “0” (Low) for
mode). Each packet represents 32 cycles of SPM frequency. The window
a detected tone and a logic “1” (High) for N
OTONE
detection. See Figure 7.
is a shifting window,
ie. the 48ms window is assessed every 2ms (16Khz mode) or 2.667ms (12Khz). If the necessary
number of good packets are consecutive, the output will respond in the minimum time of 40ms.
21
15
System:
The logic input to select device operation to either 12kHz (logic “1” - High) or 16kHz
(logic “0” - Low) SPM systems. This input has an internal 1MΩ pullup resistor (12kHz).
· logic 0 represents ‘detect’ and logic 1 represents ‘not detect’.
24
16
V
DD
:
Positive supply rail. A single, stable power supply is required. Critical levels and voltages
within the FX631 are dependant upon this supply. This pin should be decoupled to V
SS
by a capacitor mounted close to the pin.
Note that if this device is ‘line’ powered, the resulting supply must be stable. See notes on
Microcircuit Protection from high and spurious line voltages.
2, 3, 7, 5, 6,
9, 10,
12
11, 14,
15, 16,
22, 23
No internal connection, leave open circuit.
2
CMLMICRO [ CML MICROCIRCUITS ]
