Pin Number
DIL
FX621P
Quad
FX621LG/LS
Function
1
1
Xtal/Clock:
Input to the clock oscillator inverter. A single 4.433619MHz Xtal or external clock
pulse input is required (see Figure 2).
V
DD
:
The positive supply rail. A single, stable supply in the range 3.5V to 5V is required.
Detector Input:
“Schmitt Trigger” level detector circuitry whose input thresholds are set
internally and dependent on the applied V
DD
. For use with low signal-level systems this input
should be preceded by the “System Gain Set” amplifier. To use this input without the “System
Gain Set” amplifier, the components indicated in Figure 2 (inset) should be used with the
protection diodes (D
1
- D
4
).
Amplifier Input (+):
The positive and negative inputs to the “System Gain Set” Amplifier.
With single or differential inputs this amplifier and its external circuitry
can be used to provide the extra gain required to set the device to the
user’s National Level Specification. External diodes are used at both
inputs (if in use) to provide protection when the line input level exceeds
the supply rails (above the Absolute Maximum Rating).
If this device is used without this amplifier, the protection diodes should
be employed at the Detector Input. See Figure 2.
2
3
2
5
4
6
5
7
Amplifier Input (–):
6
8
Amplifier Output:
The output of the “System Gain Set” Amplifier, is used with gain setting
components. See Figures 1 and 2.
V
SS
:
The negative supply rail, (GND).
V
BIAS
:
The internal analogue bias pin, this point is at V
DD
/2 and requires to be externally
decoupled to V
SS
via capacitor C
3
.
Space Length Time:
Active only in the ‘SPM Packet’ mode, this input, with an external RC
network, sets the minimum valid No-Tone (Space) period for the incoming packet using the
formula: t
S
= 0.7 (R
6
x C
5
). If the ‘SPM Packet’ mode is not required these timing components
may be omitted. See Page 4.
Pulse Length Time:
Active only in the ‘SPM Packet’ mode, this input, with an external RC
network, sets the minimum valid Tone period for the incoming packet using the formula:
t
M
= 0.7 (R
5
x C
4
). If the ‘SPM Packet’ mode is not required these timing components may be
omitted. See Page 4.
Output Reset:
This input is used only in the ‘SPM Packet’ mode. Once an SPM packet has
been detected and an output generated (logic “0”) from this device the output remains as set
until this input is strobed to a logic “0.” See Figure 3. This input has an internal 1MΩ pullup
resistor.
Mode Select:
A control pin to select either the ‘Tone Follower’ mode or the ‘SPM Packet’ mode.
A logic “1” selects ‘Tone Follower’, a logic “0” selects ‘SPM Packet.’ This input has an internal
1MΩ pullup resistor (Tone Follower).
Output:
The digital output of the SPM Detector. In the ‘Tone Follower’ mode a valid tone gives
a logic “0” and no-tone gives a logic “1.” Tonebursts and tone dropouts of less than 16 cycles
are ignored. In the ‘SPM Packet’ mode the output is set to a logic “0” when a valid ‘packet’ is
measured. The output remains as set until reset by a logic “0” at the Output Reset function,
see Figure 3.
System Select:
A control pin to set the device to work on either a 12kHz (logic “1”) or 16kHz
(logic “0”) SPM system. This input has an internal 1MΩ pullup resistor (12kHz).
Xtal:
The output of the clock oscillator inverter, see Figure 2.
8
9
12
13
10
14
11
17
12
18
13
19
14
20
15
23
16
24
3, 4, 9, 10,
11, 15, 16,
21, 22.
7
No internal connection – leave open circuit.
2
CMLMICRO [ CML MICROCIRCUITS ]
